format code

[soc.git] / src / soc / fu / alu / formal / proof_output_stage.py

diff --git a/src/soc/fu/alu/formal/proof_output_stage.py b/src/soc/fu/alu/formal/proof_output_stage.py
index 5e32fbfde9d84e0c91dbf5a0171edae5a95f9f7d..e20aa1ebd2cf5f4381b3ad16e0a479ca2345b589 100644 (file)
--- a/src/soc/fu/alu/formal/proof_output_stage.py
+++ b/src/soc/fu/alu/formal/proof_output_stage.py
@@ -103,11 +103,13 @@ class Driver(Elaboratable):
 
         return m
 
+
 class GTCombinerTestCase(FHDLTestCase):
     def test_formal(self):
         module = Driver()
         self.assertFormal(module, mode="bmc", depth=4)
         self.assertFormal(module, mode="cover", depth=4)
+
     def test_ilang(self):
         dut = Driver()
         vl = rtlil.convert(dut, ports=[])