add parent_pspec everywhere

[soc.git] / src / soc / fu / alu / formal / proof_output_stage.py

diff --git a/src/soc/fu/alu/formal/proof_output_stage.py b/src/soc/fu/alu/formal/proof_output_stage.py
index e20aa1ebd2cf5f4381b3ad16e0a479ca2345b589..eb6f45719553b8545111595cb0d7964a7a45872f 100644 (file)
--- a/src/soc/fu/alu/formal/proof_output_stage.py
+++ b/src/soc/fu/alu/formal/proof_output_stage.py
@@ -38,7 +38,7 @@ class Driver(Elaboratable):
             recwidth += width
             comb += p.eq(AnyConst(width))
 
-        pspec = ALUPipeSpec(id_wid=2)
+        pspec = ALUPipeSpec(id_wid=2, parent_pspec=None)
         m.submodules.dut = dut = ALUOutputStage(pspec)
 
         o = Signal(64)