add parent_pspec everywhere
[soc.git] / src / soc / fu / branch / formal / proof_main_stage.py
index 5d940b1ad873992c33890bb86b74526a0b5ca54e..0f58e1c049d130e3cc1b46ddccd0bbbc1a6f53dc 100644 (file)
@@ -39,7 +39,7 @@ class Driver(Elaboratable):
             recwidth += width
             comb += p.eq(AnyConst(width))
 
-        pspec = BranchPipeSpec(id_wid=2)
+        pspec = BranchPipeSpec(id_wid=2, parent_pspec=None)
         m.submodules.dut = dut = BranchMainStage(pspec)
 
         # convenience aliases