else:
core_final = ()
div_out = DivOutputStage(self.pspec)
- alu_out = DivMulOutputStage(self.pspec)
self.div_out = div_out # debugging - bug #425
- return [*core_final, div_out, alu_out]
+ return [*core_final, div_out]
+
+
+class DivStagesFinalise(PipeModBaseChain):
+ def get_chain(self):
+ alu_out = DivMulOutputStage(self.pspec)
+ return [alu_out]
class DivBasePipe(ControlBase):
self.pipe_middles.append(
self.pspec.div_pipe_kind.config.core_stage_class(pspec))
self.pipe_end = DivStagesEnd(pspec)
+ self.pipe_final = DivStagesFinalise(pspec)
self._eqs = self.connect([self.pipe_start,
*self.pipe_middles,
- self.pipe_end])
+ self.pipe_end,
+ self.pipe_final])
def elaborate(self, platform):
m = ControlBase.elaborate(self, platform)
m.submodules.pipe_start = self.pipe_start
- for i in self.pipe_middles:
- name = f"pipe_{i.stage_start_index}_to_{i.stage_end_index}"
- setattr(m.submodules, name, i)
+ for i in range(len(self.pipe_middles)):
+ name = f"pipe_middle_{i}"
+ setattr(m.submodules, name, self.pipe_middles[i])
m.submodules.pipe_end = self.pipe_end
+ m.submodules.pipe_final = self.pipe_final
m.d.comb += self._eqs
return m