import unittest
import power_instruction_analyzer as pia
from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import XER_bits, Function
-from soc.decoder.isa.all import ISA
-from soc.config.endian import bigendian
-
-from soc.fu.test.common import ALUHelpers
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Delay
+
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_enums import XER_bits, Function
+from openpower.decoder.isa.all import ISA
+from openpower.endian import bigendian
+
+from openpower.test.common import ALUHelpers
+from soc.fu.test.pia import pia_res_to_output
from soc.fu.div.pipeline import DivBasePipe
from soc.fu.div.pipe_data import DivPipeSpec
return res
-def pia_res_to_output(pia_res):
- retval = {}
- if pia_res.rt is not None:
- retval["o"] = pia_res.rt
- if pia_res.cr0 is not None:
- cr0 = pia_res.cr0
- v = 0
- if cr0.lt:
- v |= 8
- if cr0.gt:
- v |= 4
- if cr0.eq:
- v |= 2
- if cr0.so:
- v |= 1
- retval["cr_a"] = v
- if pia_res.overflow is not None:
- overflow = pia_res.overflow
- v = 0
- if overflow.ov:
- v |= 1
- if overflow.ov32:
- v |= 2
- retval["xer_ov"] = v
- retval["xer_so"] = overflow.so
- else:
- retval["xer_ov"] = 0
- retval["xer_so"] = 0
- return retval
-
-
def set_alu_inputs(alu, dec2, sim):
# TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
# detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
- # and place it into data_i.b
+ # and place it into i_data.b
inp = yield from get_cu_inputs(dec2, sim)
yield from ALUHelpers.set_int_ra(alu, dec2, inp)
# note that it is critically important to do this
# for DIV otherwise it starts trying to produce
# multiple results.
- yield alu.p.valid_i.eq(1)
+ yield alu.p.i_valid.eq(1)
yield
- yield alu.p.valid_i.eq(0)
+ yield alu.p.i_valid.eq(0)
opname = code.split(' ')[0]
fnname = opname.replace(".", "_")
yield from isa_sim.call(opname)
index = isa_sim.pc.CIA.value//4
- vld = yield alu.n.valid_o
+ vld = yield alu.n.o_valid
while not vld:
yield
yield Delay(0.1e-6)
- # XXX sim._state is an internal variable
+ # XXX sim._engine is an internal variable
# Waiting on https://github.com/nmigen/nmigen/issues/443
try:
- print(f"time: {sim._state.timeline.now * 1e6}us")
+ print(f"time: {sim._engine.now * 1e6}us")
except AttributeError:
pass
- vld = yield alu.n.valid_o
+ vld = yield alu.n.o_valid
# bug #425 investigation
do = alu.pipe_end.div_out
ctx_op = do.i.ctx.op
print("")
yield Delay(0.1e-6)
- # XXX sim._state is an internal variable
+ # XXX sim._engine is an internal variable
# Waiting on https://github.com/nmigen/nmigen/issues/443
try:
- print(f"check time: {sim._state.timeline.now * 1e6}us")
+ print(f"check time: {sim._engine.now * 1e6}us")
except AttributeError:
pass
msg = "%s: %s" % (div_pipe_kind.name, code)
- msg += " %s" % (repr(prog.assembly))
- msg += " %s" % (repr(test.regs))
+ msg += f" {prog.assembly!r} {list(map(hex, test.regs))!r}"
yield from self.check_alu_outputs(alu, pdecode2,
isa_sim, msg,
pia_res)
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- pspec = DivPipeSpec(id_wid=2, div_pipe_kind=div_pipe_kind)
+ class PPspec:
+ XLEN = 64
+ pps = PPspec()
+ pspec = DivPipeSpec(
+ id_wid=2, div_pipe_kind=div_pipe_kind, parent_pspec=pps)
m.submodules.alu = alu = DivBasePipe(pspec)
- comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
- comb += alu.n.ready_i.eq(1)
+ comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
+ comb += alu.n.i_ready.eq(1)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
sim = Simulator(m)
print("oe, oe_ok", oe, oe_ok)
if not oe or not oe_ok:
# if OE not enabled, XER SO and OV must not be activated
- so_ok = yield alu.n.data_o.xer_so.ok
- ov_ok = yield alu.n.data_o.xer_ov.ok
+ so_ok = yield alu.n.o_data.xer_so.ok
+ ov_ok = yield alu.n.o_data.xer_ov.ok
print("so, ov", so_ok, ov_ok)
self.assertEqual(ov_ok, False, code)
self.assertEqual(so_ok, False, code)
projects / soc.git / blobdiff