set parent pspec to class with XLEN = 64

[soc.git] / src / soc / fu / div / test / helper.py

diff --git a/src/soc/fu/div/test/helper.py b/src/soc/fu/div/test/helper.py
index 5be75e64b9c4fc58901926ac15d8bf3272977273..3a854975b1aa2b4999fcdd2ee6c3789a96c38847 100644 (file)
--- a/src/soc/fu/div/test/helper.py
+++ b/src/soc/fu/div/test/helper.py
@@ -7,13 +7,13 @@ from nmigen import Module, Signal
 # Also, check out the cxxsim nmigen branch, and latest yosys from git
 from nmutil.sim_tmp_alternative import Simulator, Delay
 
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import XER_bits, Function
-from soc.decoder.isa.all import ISA
-from soc.config.endian import bigendian
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_enums import XER_bits, Function
+from openpower.decoder.isa.all import ISA
+from openpower.endian import bigendian
 
-from soc.fu.test.common import ALUHelpers
+from openpower.test.common import ALUHelpers
 from soc.fu.test.pia import pia_res_to_output
 from soc.fu.div.pipeline import DivBasePipe
 from soc.fu.div.pipe_data import DivPipeSpec
@@ -41,7 +41,7 @@ def get_cu_inputs(dec2, sim):
 def set_alu_inputs(alu, dec2, sim):
     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
-    # and place it into data_i.b
+    # and place it into i_data.b
 
     inp = yield from get_cu_inputs(dec2, sim)
     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
@@ -95,9 +95,9 @@ class DivTestHelper(unittest.TestCase):
             # note that it is critically important to do this
             # for DIV otherwise it starts trying to produce
             # multiple results.
-            yield alu.p.valid_i.eq(1)
+            yield alu.p.i_valid.eq(1)
             yield
-            yield alu.p.valid_i.eq(0)
+            yield alu.p.i_valid.eq(0)
 
             opname = code.split(' ')[0]
             fnname = opname.replace(".", "_")
@@ -109,7 +109,7 @@ class DivTestHelper(unittest.TestCase):
             yield from isa_sim.call(opname)
             index = isa_sim.pc.CIA.value//4
 
-            vld = yield alu.n.valid_o
+            vld = yield alu.n.o_valid
             while not vld:
                 yield
                 yield Delay(0.1e-6)
@@ -119,7 +119,7 @@ class DivTestHelper(unittest.TestCase):
                     print(f"time: {sim._engine.now * 1e6}us")
                 except AttributeError:
                     pass
-                vld = yield alu.n.valid_o
+                vld = yield alu.n.o_valid
                 # bug #425 investigation
                 do = alu.pipe_end.div_out
                 ctx_op = do.i.ctx.op
@@ -163,11 +163,15 @@ class DivTestHelper(unittest.TestCase):
 
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 
-        pspec = DivPipeSpec(id_wid=2, div_pipe_kind=div_pipe_kind)
+        class PPspec:
+            XLEN = 64
+        pps = PPspec()
+        pspec = DivPipeSpec(
+            id_wid=2, div_pipe_kind=div_pipe_kind, parent_pspec=pps)
         m.submodules.alu = alu = DivBasePipe(pspec)
 
-        comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do)
-        comb += alu.n.ready_i.eq(1)
+        comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
+        comb += alu.n.i_ready.eq(1)
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
         sim = Simulator(m)
 
@@ -232,8 +236,8 @@ class DivTestHelper(unittest.TestCase):
         print("oe, oe_ok", oe, oe_ok)
         if not oe or not oe_ok:
             # if OE not enabled, XER SO and OV must not be activated
-            so_ok = yield alu.n.data_o.xer_so.ok
-            ov_ok = yield alu.n.data_o.xer_ov.ok
+            so_ok = yield alu.n.o_data.xer_so.ok
+            ov_ok = yield alu.n.o_data.xer_ov.ok
             print("so, ov", so_ok, ov_ok)
             self.assertEqual(ov_ok, False, code)
             self.assertEqual(so_ok, False, code)