format code

[soc.git] / src / soc / fu / logical / formal / proof_input_stage.py

diff --git a/src/soc/fu/logical/formal/proof_input_stage.py b/src/soc/fu/logical/formal/proof_input_stage.py
index d11f832df0b7e4d68957e85c40e83ca013b5aaf8..b0b70d381aa69eecb46c802de055d4cc72de581b 100644 (file)
--- a/src/soc/fu/logical/formal/proof_input_stage.py
+++ b/src/soc/fu/logical/formal/proof_input_stage.py
@@ -41,7 +41,7 @@ class Driver(Elaboratable):
                  dut.i.b.eq(b),
                  a.eq(AnyConst(64)),
                  b.eq(AnyConst(64))]
-                      
+
         comb += dut.i.ctx.op.eq(rec)
 
         # Assert that op gets copied from the input to output
@@ -70,6 +70,7 @@ class GTCombinerTestCase(FHDLTestCase):
         module = Driver()
         self.assertFormal(module, mode="bmc", depth=4)
         self.assertFormal(module, mode="cover", depth=4)
+
     def test_ilang(self):
         dut = Driver()
         vl = rtlil.convert(dut, ports=[])