add parent_pspec everywhere

[soc.git] / src / soc / fu / mmu / test / test_pipe_caller.py

diff --git a/src/soc/fu/mmu/test/test_pipe_caller.py b/src/soc/fu/mmu/test/test_pipe_caller.py
index 70c853ebf172b61b5299949ddbd1e26c19d69316..8f36cfd8ae82cfc1eaafdcc4735a2b448f84dc64 100644 (file)
--- a/src/soc/fu/mmu/test/test_pipe_caller.py
+++ b/src/soc/fu/mmu/test/test_pipe_caller.py
@@ -73,7 +73,7 @@ def check_fsm_outputs(fsm, pdecode2, sim, code):
 
 class MMUIlangCase(TestAccumulatorBase):
     # def case_ilang(self):
-    #    pspec = SPRPipeSpec(id_wid=2)
+    #    pspec = SPRPipeSpec(id_wid=2, parent_pspec=None)
     #    alu = SPRBasePipe(pspec)
     #    vl = rtlil.convert(alu, ports=alu.ports())
     #    with open("trap_pipeline.il", "w") as f:
@@ -220,7 +220,7 @@ class TestRunner(unittest.TestCase):
 
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 
-        pipe_spec = MMUPipeSpec(id_wid=2)
+        pipe_spec = MMUPipeSpec(id_wid=2, parent_pspec=None)
         ldst = LoadStore1(pspec)
         fsm = FSMMMUStage(pipe_spec)
         fsm.set_ldst_interface(ldst)