add parent_pspec everywhere

[soc.git] / src / soc / fu / shift_rot / formal / proof_main_stage.py

diff --git a/src/soc/fu/shift_rot/formal/proof_main_stage.py b/src/soc/fu/shift_rot/formal/proof_main_stage.py
index 4528de0a4cb8cb3649674adb392eeee9c0cfb4ce..74b4d7db48e56e590189e062916654630ddb0c8a 100644 (file)
--- a/src/soc/fu/shift_rot/formal/proof_main_stage.py
+++ b/src/soc/fu/shift_rot/formal/proof_main_stage.py
@@ -54,7 +54,7 @@ class Driver(Elaboratable):
         comb += rec.is_signed.eq(AnyConst(rec.is_signed.width))
         comb += rec.insn.eq(AnyConst(rec.insn.width))
 
-        pspec = ShiftRotPipeSpec(id_wid=2)
+        pspec = ShiftRotPipeSpec(id_wid=2, parent_pspec=None)
         m.submodules.dut = dut = ShiftRotMainStage(pspec)
 
         # convenience variables