Links:
* https://bugs.libre-soc.org/show_bug.cgi?id=348
* https://libre-soc.org/openpower/isa/sprset/
+* https://libre-soc.org/3d_gpu/architecture/regfile/
"""
-from nmigen import Signal, Const
-from ieee754.fpcommon.getop import FPPipeContext
-from soc.fu.pipe_data import IntegerData
-from soc.decoder.power_decoder2 import Data
+from soc.fu.pipe_data import FUBaseData
from soc.fu.spr.spr_input_record import CompSPROpSubset
+from soc.fu.alu.pipe_data import CommonPipeSpec
-class SPRInputData(IntegerData):
+class SPRInputData(FUBaseData):
regspec = [('INT', 'ra', '0:63'), # RA
('SPR', 'spr1', '0:63'), # SPR (slow)
- ('FAST', 'spr2', '0:63'), # SPR (fast: MSR, LR, CTR etc)
+ ('FAST', 'fast1', '0:63'), # SPR (fast: LR, CTR etc)
+ ('STATE', 'state1', '0:63'), # SPR (DEC/TB)
('XER', 'xer_so', '32'), # XER bit 32: SO
('XER', 'xer_ov', '33,44'), # XER bit 34/45: CA/CA32
('XER', 'xer_ca', '34,45')] # bit0: ov, bit1: ov32
# convenience
self.a = self.ra
+# note that state1 gets a corresponding "state1" write port created
+# by core.py which is "monitored" by TestIssuerBase (hack-job, sigh).
+# when writes are spotted then the DEC/TB FSM resets and re-reads
+# DEC/TB.
-class SPROutputData(IntegerData):
+class SPROutputData(FUBaseData):
regspec = [('INT', 'o', '0:63'), # RT
('SPR', 'spr1', '0:63'), # SPR (slow)
- ('FAST', 'spr2', '0:63'), # SPR (fast: MSR, LR, CTR etc)
+ ('FAST', 'fast1', '0:63'), # SPR (fast: LR, CTR etc)
+ ('STATE', 'state1', '0:63'), # SPR (DEC/TB)
('XER', 'xer_so', '32'), # XER bit 32: SO
('XER', 'xer_ov', '33,44'), # XER bit 34/45: CA/CA32
('XER', 'xer_ca', '34,45')] # bit0: ov, bit1: ov32
super().__init__(pspec, True)
-class SPRPipeSpec:
- regspec = (SPRInputData.regspec, SPROutputData.regspec)
+class SPRPipeSpec(CommonPipeSpec):
+ regspecklses = (SPRInputData, SPROutputData)
opsubsetkls = CompSPROpSubset
- def __init__(self, id_wid, op_wid):
- self.id_wid = id_wid
- self.op_wid = op_wid
- self.opkls = lambda _: self.opsubsetkls(name="op")
- self.stage = None
- self.pipekls = SimpleHandshakeRedir