add parent_pspec everywhere
[soc.git] / src / soc / fu / trap / formal / proof_main_stage.py
index c00a3fbff4a199b21be6ff5a82da9e754af2c7eb..b94f7e732d255cc5aa1a063e012c9edd354a1c79 100644 (file)
@@ -37,7 +37,7 @@ class Driver(Elaboratable):
         comb = m.d.comb
 
         rec = CompTrapOpSubset()
-        pspec = TrapPipeSpec(id_wid=2)
+        pspec = TrapPipeSpec(id_wid=2, parent_pspec=None)
 
         m.submodules.dut = dut = TrapMainStage(pspec)