(pspec.microwatt_compat == True))
self.alt_reset = Signal(reset_less=True) # not connected yet (microwatt)
+ if self.microwatt_compat:
+ self.microwatt_old = False
+ self.microwatt_debug = True # set to False when using an FPGA
+
# test is SVP64 is to be enabled
self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
self.srcmask = Signal(64)
self.dstmask = Signal(64)
- # sigh, the wishbone addresses are not wishbone-compliant in microwatt
+ # sigh, the wishbone addresses are not wishbone-compliant
+ # in old versions of microwatt, tplaten_3d_game is a new one
if self.microwatt_compat:
self.ibus_adr = Signal(32, name='wishbone_insn_out.adr')
self.dbus_adr = Signal(32, name='wishbone_data_out.adr')
if self.dbg_domain != 'sync':
comb += dbgclk.eq(ClockSignal())
+ # if using old version of microwatt
# drop the first 3 bits of the incoming wishbone addresses
- # this can go if using later versions of microwatt (not now)
if self.microwatt_compat:
ibus = self.imem.ibus
dbus = self.core.l0.cmpi.wb_bus()
- comb += self.ibus_adr.eq(Cat(Const(0, 3), ibus.adr))
- comb += self.dbus_adr.eq(Cat(Const(0, 3), dbus.adr))
- # microwatt verilator debug purposes
- pi = self.core.l0.cmpi.pi.pi
- comb += self.ldst_req.eq(pi.addr_ok_o)
- comb += self.ldst_addr.eq(pi.addr)
+ if self.microwatt_old:
+ comb += self.ibus_adr.eq(Cat(Const(0, 3), ibus.adr))
+ comb += self.dbus_adr.eq(Cat(Const(0, 3), dbus.adr))
+ else:
+ comb += self.ibus_adr.eq(ibus.adr)
+ comb += self.dbus_adr.eq(dbus.adr)
+ if self.microwatt_debug:
+ # microwatt verilator debug purposes
+ pi = self.core.l0.cmpi.pi.pi
+ comb += self.ldst_req.eq(pi.addr_ok_o)
+ comb += self.ldst_addr.eq(pi.addr)
cur_state = self.cur_state
# reset current state if core reset requested
with m.If(core_rst):
m.d.sync += self.cur_state.eq(0)
+ # and, sigh, set configured values, which are also done in regfile
+ # XXX ??? what the hell is the shift for??
+ m.d.sync += self.cur_state.pc.eq(self.core.pc_at_reset)
+ m.d.sync += self.cur_state.msr.eq(self.core.msr_at_reset)
# check halted condition: requested PC to execute matches DMI stop addr
# and immediately stop. address of 0xffff_ffff_ffff_ffff can never
easy understanding) come later.
"""
- def fetch_fsm(self, m, dbg, core, pc, msr, svstate, nia, is_svp64_mode,
+ def fetch_fsm(self, m, dbg, core, core_rst, nia, is_svp64_mode,
fetch_pc_o_ready, fetch_pc_i_valid,
fetch_insn_o_valid, fetch_insn_i_ready):
"""fetch FSM
pdecode2 = self.pdecode2
cur_state = self.cur_state
dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
+ pc, msr, svstate = cur_state.pc, cur_state.msr, cur_state.svstate
# also note instruction fetch failed
if hasattr(core, "icache"):
fetch_failed = Const(0, 1)
flush_needed = False
- # create a register with pc+4 as a way to reduce combinatorial chains
- pc4 = Signal.like(cur_state.pc)
- sync += pc4.eq(cur_state.pc + 4)
-
# set priv / virt mode on I-Cache, sigh
if isinstance(self.imem, ICache):
comb += self.imem.i_in.priv_mode.eq(~msr[MSR.PR])
# allow fetch to not run at startup due to I-Cache reset not
# having time to settle. power-on-reset holds dbg.core_stopped_i
with m.State("PRE_IDLE"):
- with m.If(~dbg.core_stopped_i & ~dbg.core_stop_o):
+ with m.If(~dbg.core_stopped_i & ~dbg.core_stop_o & ~core_rst):
m.next = "IDLE"
# waiting (zzz)
comb += self.imem.a_pc_i.eq(pc)
comb += self.imem.a_i_valid.eq(1)
comb += self.imem.f_i_valid.eq(1)
- # transfer state to output
- sync += cur_state.pc.eq(pc)
- sync += cur_state.svstate.eq(svstate) # and svstate
- sync += cur_state.msr.eq(msr) # and msr
-
m.next = "INSN_READ" # move to "wait for bus" phase
# dummy pause to find out why simulation is not keeping up
m.next = "INSN_READY"
with m.Else():
# fetch the rest of the instruction from memory
- comb += self.imem.a_pc_i.eq(pc4)
+ comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
comb += self.imem.a_i_valid.eq(1)
comb += self.imem.f_i_valid.eq(1)
m.next = "INSN_READ2"
# blech, icache returns actual instruction
insn = self.imem.f_instr_o
else:
- insn = get_insn(self.imem.f_instr_o, pc4)
+ insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
sync += dec_opcode_i.eq(insn)
m.next = "INSN_READY"
# TODO: probably can start looking at pdecode2.rm_dec
fetch_failed = Const(0, 1)
flush_needed = False
+ sync += fetch_pc_i_valid.eq(0)
+
with m.FSM(name="issue_fsm"):
+ with m.State("PRE_IDLE"):
+ with m.If(~dbg.core_stop_o & ~core_rst):
+ m.next = "ISSUE_START"
+
# sync with the "fetch" phase which is reading the instruction
# at this point, there is no instruction running, that
# could inadvertently update the PC.
# wait on "core stop" release, before next fetch
# need to do this here, in case we are in a VL==0 loop
with m.If(~dbg.core_stop_o & ~core_rst):
- comb += fetch_pc_i_valid.eq(1) # tell fetch to start
+ sync += fetch_pc_i_valid.eq(1) # tell fetch to start
+ sync += cur_state.pc.eq(dbg.state.pc)
+ sync += cur_state.svstate.eq(dbg.state.svstate)
+ sync += cur_state.msr.eq(dbg.state.msr)
with m.If(fetch_pc_o_ready): # fetch acknowledged us
m.next = "INSN_WAIT"
with m.Else():
# Issue is where the VL for-loop # lives. the ready/valid
# signalling is used to communicate between the four.
- self.fetch_fsm(m, dbg, core, dbg.state.pc, dbg.state.msr,
- dbg.state.svstate, nia, is_svp64_mode,
+ self.fetch_fsm(m, dbg, core, core_rst, nia, is_svp64_mode,
fetch_pc_o_ready, fetch_pc_i_valid,
fetch_insn_o_valid, fetch_insn_i_ready)
exec_insn_i_valid, exec_insn_o_ready,
exec_pc_o_valid, exec_pc_i_ready)
- # whatever was done above, over-ride it if core reset is held
+ # whatever was done above, over-ride it if core reset is held.
+ # set NIA to pc_at_reset
with m.If(core_rst):
- sync += nia.eq(0)
+ sync += nia.eq(self.core.pc_at_reset)
return m
projects / soc.git / blobdiff