(pspec.microwatt_compat == True))
self.alt_reset = Signal(reset_less=True) # not connected yet (microwatt)
+ if self.microwatt_compat:
+ self.microwatt_old = False
+ self.microwatt_debug = True # set to False when using an FPGA
+
# test is SVP64 is to be enabled
self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
# hack method of keeping an eye on whether branch/trap set the PC
self.state_nia = self.core.regs.rf['state'].w_ports['nia']
self.state_nia.wen.name = 'state_nia_wen'
+ # and whether SPR pipeline sets DEC or TB
+ self.state_spr = self.core.regs.rf['state'].w_ports['state1']
# pulse to synchronize the simulator at instruction end
self.insn_done = Signal()
self.srcmask = Signal(64)
self.dstmask = Signal(64)
- # sigh, the wishbone addresses are not wishbone-compliant in microwatt
+ # sigh, the wishbone addresses are not wishbone-compliant
+ # in old versions of microwatt, tplaten_3d_game is a new one
if self.microwatt_compat:
self.ibus_adr = Signal(32, name='wishbone_insn_out.adr')
self.dbus_adr = Signal(32, name='wishbone_data_out.adr')
if self.dbg_domain != 'sync':
comb += dbgclk.eq(ClockSignal())
+ # if using old version of microwatt
# drop the first 3 bits of the incoming wishbone addresses
- # this can go if using later versions of microwatt (not now)
if self.microwatt_compat:
ibus = self.imem.ibus
dbus = self.core.l0.cmpi.wb_bus()
- comb += self.ibus_adr.eq(Cat(Const(0, 3), ibus.adr))
- comb += self.dbus_adr.eq(Cat(Const(0, 3), dbus.adr))
- # microwatt verilator debug purposes
- pi = self.core.l0.cmpi.pi.pi
- comb += self.ldst_req.eq(pi.addr_ok_o)
- comb += self.ldst_addr.eq(pi.addr)
+ if self.microwatt_old:
+ comb += self.ibus_adr.eq(Cat(Const(0, 3), ibus.adr))
+ comb += self.dbus_adr.eq(Cat(Const(0, 3), dbus.adr))
+ else:
+ comb += self.ibus_adr.eq(ibus.adr)
+ comb += self.dbus_adr.eq(dbus.adr)
+ if self.microwatt_debug:
+ # microwatt verilator debug purposes
+ pi = self.core.l0.cmpi.pi.pi
+ comb += self.ldst_req.eq(pi.addr_ok_o)
+ comb += self.ldst_addr.eq(pi.addr)
cur_state = self.cur_state
m.submodules["sram4k_%d" % i] = csd(sram)
comb += sram.enable.eq(self.wb_sram_en)
- # terrible hack to stop a potential race condition. if core
- # is doing any operation (at all) pause the DEC/TB FSM
- comb += self.pause_dec_tb.eq(core.pause_dec_tb)
-
# XICS interrupt handler
if self.xics:
m.submodules.xics_icp = icp = csd(self.xics_icp)
dbg_sync = ClockDomain(self.dbg_domain)
m.domains += dbg_sync
+ # create a delay, but remember it is in the power-on-reset clock domain!
ti_rst = Signal(reset_less=True)
delay = Signal(range(4), reset=3)
+ stop_delay = Signal(range(16), reset=5)
with m.If(delay != 0):
- m.d.por += delay.eq(delay - 1)
+ m.d.por += delay.eq(delay - 1) # decrement... in POR domain!
+ with m.If(stop_delay != 0):
+ m.d.por += stop_delay.eq(stop_delay - 1) # likewise
comb += cd_por.clk.eq(ClockSignal())
# power-on reset delay
else:
with m.If(delay != 0 | dbg.core_rst_o):
comb += core_rst.eq(1)
+ with m.If(stop_delay != 0):
+ # run DMI core-stop as well but on an extra couple of cycles
+ comb += dbg.core_stopped_i.eq(1)
# connect external reset signal to DMI Reset
if self.dbg_domain != "sync":
comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
# temporary hack: says "go" immediately for both address gen and ST
+ # XXX: st.go_i is set to 1 cycle delay to reduce combinatorial chains
l0 = core.l0
ldst = core.fus.fus['ldst0']
st_go_edge = rising_edge(m, ldst.st.rel_o)
# link addr-go direct to rel
m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o)
- m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
+ m.d.sync += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
def do_dmi(self, m, dbg):
"""deals with DMI debug requests
value to DEC, however the regfile has "passthrough" on it so this
*should* be ok.
- see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
+ see v3.0B p1097-1099 for Timer Resource and p1065 and p1076
"""
comb, sync = m.d.comb, m.d.sync
- fast_rf = self.core.regs.rf['fast']
- fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
- fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
+ state_rf = self.core.regs.rf['state']
+ state_r_dectb = state_rf.r_ports['issue'] # DEC/TB
+ state_w_dectb = state_rf.w_ports['issue'] # DEC/TB
with m.FSM() as fsm:
# initiates read of current DEC
with m.State("DEC_READ"):
- comb += fast_r_dectb.addr.eq(FastRegs.DEC)
- comb += fast_r_dectb.ren.eq(1)
+ comb += state_r_dectb.ren.eq(1<<StateRegs.DEC)
with m.If(~self.pause_dec_tb):
m.next = "DEC_WRITE"
with m.Else():
new_dec = Signal(64)
# TODO: MSR.LPCR 32-bit decrement mode
- comb += new_dec.eq(fast_r_dectb.o_data - 1)
- comb += fast_w_dectb.addr.eq(FastRegs.DEC)
- comb += fast_w_dectb.wen.eq(1)
- comb += fast_w_dectb.i_data.eq(new_dec)
+ comb += new_dec.eq(state_r_dectb.o_data - 1)
+ comb += state_w_dectb.wen.eq(1<<StateRegs.DEC)
+ comb += state_w_dectb.i_data.eq(new_dec)
# copy to cur_state for decoder, for an interrupt
sync += spr_dec.eq(new_dec)
m.next = "TB_READ"
# initiates read of current TB
with m.State("TB_READ"):
- comb += fast_r_dectb.addr.eq(FastRegs.TB)
- comb += fast_r_dectb.ren.eq(1)
+ comb += state_r_dectb.ren.eq(1<<StateRegs.TB)
with m.If(~self.pause_dec_tb):
m.next = "TB_WRITE"
m.next = "TB_READ"
with m.Else():
new_tb = Signal(64)
- comb += new_tb.eq(fast_r_dectb.o_data + 1)
- comb += fast_w_dectb.addr.eq(FastRegs.TB)
- comb += fast_w_dectb.wen.eq(1)
- comb += fast_w_dectb.i_data.eq(new_tb)
+ comb += new_tb.eq(state_r_dectb.o_data + 1)
+ comb += state_w_dectb.wen.eq(1<<StateRegs.TB)
+ comb += state_w_dectb.i_data.eq(new_tb)
m.next = "DEC_READ"
return m
# reset current state if core reset requested
with m.If(core_rst):
m.d.sync += self.cur_state.eq(0)
+ # and, sigh, set configured values, which are also done in regfile
+ # XXX ??? what the hell is the shift for??
+ m.d.sync += self.cur_state.pc.eq(self.core.pc_at_reset)
+ m.d.sync += self.cur_state.msr.eq(self.core.msr_at_reset)
# check halted condition: requested PC to execute matches DMI stop addr
# and immediately stop. address of 0xffff_ffff_ffff_ffff can never
easy understanding) come later.
"""
- def fetch_fsm(self, m, dbg, core, pc, msr, svstate, nia, is_svp64_mode,
+ def fetch_fsm(self, m, dbg, core, core_rst, nia, is_svp64_mode,
fetch_pc_o_ready, fetch_pc_i_valid,
fetch_insn_o_valid, fetch_insn_i_ready):
"""fetch FSM
pdecode2 = self.pdecode2
cur_state = self.cur_state
dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
+ pc, msr, svstate = cur_state.pc, cur_state.msr, cur_state.svstate
# also note instruction fetch failed
if hasattr(core, "icache"):
with m.FSM(name='fetch_fsm'):
+ # allow fetch to not run at startup due to I-Cache reset not
+ # having time to settle. power-on-reset holds dbg.core_stopped_i
+ with m.State("PRE_IDLE"):
+ with m.If(~dbg.core_stopped_i & ~dbg.core_stop_o & ~core_rst):
+ m.next = "IDLE"
+
# waiting (zzz)
with m.State("IDLE"):
# fetch allowed if not failed and stopped but not stepping
comb += self.imem.a_pc_i.eq(pc)
comb += self.imem.a_i_valid.eq(1)
comb += self.imem.f_i_valid.eq(1)
- # transfer state to output
- sync += cur_state.pc.eq(pc)
- sync += cur_state.svstate.eq(svstate) # and svstate
- sync += cur_state.msr.eq(msr) # and msr
-
m.next = "INSN_READ" # move to "wait for bus" phase
# dummy pause to find out why simulation is not keeping up
fetch_failed = Const(0, 1)
flush_needed = False
+ sync += fetch_pc_i_valid.eq(0)
+
with m.FSM(name="issue_fsm"):
+ with m.State("PRE_IDLE"):
+ with m.If(~dbg.core_stop_o & ~core_rst):
+ m.next = "ISSUE_START"
+
# sync with the "fetch" phase which is reading the instruction
# at this point, there is no instruction running, that
# could inadvertently update the PC.
# wait on "core stop" release, before next fetch
# need to do this here, in case we are in a VL==0 loop
with m.If(~dbg.core_stop_o & ~core_rst):
- comb += fetch_pc_i_valid.eq(1) # tell fetch to start
+ sync += fetch_pc_i_valid.eq(1) # tell fetch to start
+ sync += cur_state.pc.eq(dbg.state.pc)
+ sync += cur_state.svstate.eq(dbg.state.svstate)
+ sync += cur_state.msr.eq(dbg.state.msr)
with m.If(fetch_pc_o_ready): # fetch acknowledged us
m.next = "INSN_WAIT"
with m.Else():
# instruction started: must wait till it finishes
with m.State("INSN_ACTIVE"):
- # note changes to MSR, PC and SVSTATE
- # XXX oops, really must monitor *all* State Regfile write
- # ports looking for changes!
+ # note changes to MSR, PC and SVSTATE, and DEC/TB
+ # these last two are done together, and passed to the
+ # DEC/TB FSM
with m.If(self.state_nia.wen & (1 << StateRegs.SVSTATE)):
sync += self.sv_changed.eq(1)
with m.If(self.state_nia.wen & (1 << StateRegs.MSR)):
sync += self.msr_changed.eq(1)
with m.If(self.state_nia.wen & (1 << StateRegs.PC)):
sync += self.pc_changed.eq(1)
+ with m.If((self.state_spr.wen &
+ ((1 << StateRegs.DEC) | (1 << StateRegs.TB))).bool()):
+ comb += self.pause_dec_tb.eq(1)
with m.If(~core_busy_o): # instruction done!
comb += exec_pc_o_valid.eq(1)
with m.If(exec_pc_i_ready):
# Issue is where the VL for-loop # lives. the ready/valid
# signalling is used to communicate between the four.
- self.fetch_fsm(m, dbg, core, dbg.state.pc, dbg.state.msr,
- dbg.state.svstate, nia, is_svp64_mode,
+ self.fetch_fsm(m, dbg, core, core_rst, nia, is_svp64_mode,
fetch_pc_o_ready, fetch_pc_i_valid,
fetch_insn_o_valid, fetch_insn_i_ready)
exec_insn_i_valid, exec_insn_o_ready,
exec_pc_o_valid, exec_pc_i_ready)
- # whatever was done above, over-ride it if core reset is held
+ # whatever was done above, over-ride it if core reset is held.
+ # set NIA to pc_at_reset
with m.If(core_rst):
- sync += nia.eq(0)
+ sync += nia.eq(self.core.pc_at_reset)
return m
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