skip test_microwatt.BinaryTestCase.test_binary if file doesn't exist

[soc.git] / src / soc / simple / test / test_microwatt.py

diff --git a/src/soc/simple/test/test_microwatt.py b/src/soc/simple/test/test_microwatt.py
index 2cf0521a4dffee503977b77a580419ba2345c822..29d6acf63a05e1713c5b1c6b086c85b76af46970 100644 (file)
--- a/src/soc/simple/test/test_microwatt.py
+++ b/src/soc/simple/test/test_microwatt.py
@@ -1,5 +1,5 @@
-from soc.simulator.program import Program
-from soc.fu.test.common import TestCase
+from openpower.simulator.program import Program
+from openpower.test.common import TestCase
 
 import unittest
 
@@ -8,15 +8,19 @@ from nmigen.back.pysim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 
 from soc.simple.issuer import TestIssuer
+from openpower.endian import bigendian
+
 
 from soc.config.test.test_loadstore import TestMemPspec
 from soc.simple.test.test_core import (setup_regs, check_regs,
                                        wait_for_busy_clear,
                                        wait_for_busy_hi)
-from soc.fu.compunits.test.test_compunit import (setup_test_memory,
-                                                 check_sim_memory)
+from soc.fu.compunits.test.test_compunit import (check_sim_memory,
+                                                 get_l0_mem)
+
+from soc.simple.test.test_runner import setup_i_memory
 
-from soc.simple.test.test_issuer import setup_i_memory
+from pathlib import Path
 
 import sys
 sys.setrecursionlimit(10**6)
@@ -29,14 +33,21 @@ class BinaryTestCase(FHDLTestCase):
         super().__init__(name)
         self.test_name = name
 
+    @unittest.skip("a bit big")
+    def test_binary(self):
+        with Program("1.bin", bigendian) as program:
+            self.run_tst_program(program)
+
+    @unittest.skipUnless(Path("hello_world.bin").exists(),
+                         "missing hello_world.bin")
     def test_binary(self):
-        with Program("1.bin") as program:
+        with Program("hello_world.bin", bigendian) as program:
             self.run_tst_program(program)
 
     def run_tst_program(self, prog):
         initial_regs = [0] * 32
         tc = TestCase(prog, self.test_name, initial_regs, None, 0,
-                                            None, 0,
+                      None, 0,
                       do_sim=False)
         self.test_data.append(tc)
 
@@ -51,10 +62,11 @@ class TestRunner(FHDLTestCase):
         comb = m.d.comb
         go_insn_i = Signal()
         pc_i = Signal(32)
+        pc_i_ok = Signal()
 
         pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
                              imem_ifacetype='test_bare_wb',
-                             addr_wid=48,
+                             addr_wid=64,
                              mask_wid=8,
                              reg_wid=64,
                              imem_test_depth=32768,
@@ -66,6 +78,7 @@ class TestRunner(FHDLTestCase):
         l0 = core.l0
 
         comb += issuer.pc_i.data.eq(pc_i)
+        comb += issuer.pc_i.ok.eq(pc_i_ok)
         comb += issuer.go_insn_i.eq(go_insn_i)
 
         # nmigen Simulation
@@ -77,7 +90,7 @@ class TestRunner(FHDLTestCase):
             for test in self.test_data:
 
                 # get core going
-                yield core.bigendian_i.eq(1)
+                yield core.bigendian_i.eq(bigendian)
                 yield core.core_start_i.eq(1)
                 yield
                 yield core.core_start_i.eq(0)
@@ -86,31 +99,33 @@ class TestRunner(FHDLTestCase):
                 print(test.name)
                 program = test.program
                 self.subTest(test.name)
-                print ("regs", test.regs)
-                print ("sprs", test.sprs)
-                print ("cr", test.cr)
-                print ("mem", test.mem)
-                print ("msr", test.msr)
-                print ("assem", program.assembly)
+                print("regs", test.regs)
+                print("sprs", test.sprs)
+                print("cr", test.cr)
+                print("mem", test.mem)
+                print("msr", test.msr)
+                print("assem", program.assembly)
                 instructions = list(program.generate_instructions())
 
-                print ("instructions", len(instructions))
+                print("instructions", len(instructions))
 
-                pc = 0 # start of memory
+                pc = 0  # start of memory
 
                 yield from setup_i_memory(imem, pc, instructions)
-                #yield from setup_test_memory(l0, sim)
+                # blech!  put the same listing into the data memory
+                data_mem = get_l0_mem(l0)
+                yield from setup_i_memory(data_mem, pc, instructions)
                 yield from setup_regs(core, test)
 
                 yield pc_i.eq(pc)
-                yield issuer.pc_i.ok.eq(1)
+                yield pc_i_ok.eq(1)
 
                 while True:
 
                     # start the instruction
                     yield go_insn_i.eq(1)
                     yield
-                    yield issuer.pc_i.ok.eq(0) # don't change PC from now on
+                    yield pc_i_ok.eq(0)  # don't change PC from now on
                     yield go_insn_i.eq(0)      # and don't issue a new insn
                     yield from wait_for_busy_hi(core)
                     yield Settle()
@@ -122,21 +137,21 @@ class TestRunner(FHDLTestCase):
                     yield from wait_for_busy_clear(core)
 
                     terminated = yield core.core_terminated_o
-                    print ("terminated", terminated)
+                    print("terminated", terminated)
 
                     terminated = yield core.core_terminated_o
                     if terminated:
                         break
 
             # register check
-            #yield from check_regs(self, sim, core, test, code)
+            # yield from check_regs(self, sim, core, test, code)
 
             # Memory check
-            #yield from check_sim_memory(self, l0, sim, code)
+            # yield from check_sim_memory(self, l0, sim, code)
 
         sim.add_sync_process(process)
         with sim.write_vcd("binary_issuer_simulator.vcd",
-                            traces=[]):
+                           traces=[]):
             sim.run()
 
 
@@ -147,4 +162,3 @@ if __name__ == "__main__":
 
     runner = unittest.TextTestRunner()
     runner.run(suite)
-