from nmigen.sim import Simulator, Settle, Delay
from iomux import IOMuxBlockSingle
+from base import PinSpec
+from jtag import iotypes
io_layout = (("i", 1),
("oe", 1),
self.muxes[pad] = IOMuxBlockSingle(self.n_banks)
for mux in self.requested[pad].keys():
periph = self.requested[pad][mux][0]
- unit_num = self.requested[pad][mux][1]
- if len(self.requested[pad][mux]) == 3:
- pin = self.requested[pad][mux][2]
- else:
- pin = "io"
- if periph == "gpio":
- self.pads[pad][mux] = Record(name="gp%d" % unit_num,
+ unit = self.requested[pad][mux][1]
+ sig = self.requested[pad][mux][2][:-1]
+ sig_type = iotypes[self.requested[pad][mux][2][-1]]
+ #print(sig, sig_type)
+ if sig_type == iotypes['*']:
+ self.pads[pad][mux] = Record(name="%s%d" % (sig, unit),
layout=io_layout)
- elif periph == "uart":
- if pin == "tx":
- self.pads[pad][mux] = Record(name="tx%d" % unit_num,
- layout=uart_tx_layout)
- elif pin == "rx":
- self.pads[pad][mux] = Signal(name="rx%d" % unit_num)
- elif periph == "i2c":
- if pin == "sda":
- self.pads[pad][mux] = Record(name="sda%d" % unit_num,
- layout=io_layout)
- elif pin == "scl":
- self.pads[pad][mux] = Record(name="scl%d" % unit_num,
- layout=io_layout)
+ elif sig_type == iotypes['+']:
+ self.pads[pad][mux] = Signal(name="%s%d_o" % (sig, unit))
+ elif sig_type == iotypes['-']:
+ self.pads[pad][mux] = Signal(name="%s%d_i" % (sig, unit))
+ print(self.pads)
def elaborate(self, platform):
m = Module()
for mux in self.requested[pad].keys():
periph = self.requested[pad][mux][0]
num = int(mux[3])
- if len(self.requested[pad][mux]) == 3:
- pin = self.requested[pad][mux][2]
- else:
- pin = "io"
- if periph == "gpio" or periph == "i2c":
+ sig = self.requested[pad][mux][2][:-1]
+ sig_type = iotypes[self.requested[pad][mux][2][-1]]
+ if sig_type == iotypes['*']:
comb += muxes[pad].bank_ports[num].o.eq(pads[pad][mux].o)
comb += muxes[pad].bank_ports[num].oe.eq(pads[pad][mux].oe)
comb += pads[pad][mux].i.eq(muxes[pad].bank_ports[num].i)
- elif periph == "uart":
- if pin == "tx":
- comb += muxes[pad].bank_ports[num].o.eq(
- pads[pad][mux].o)
- comb += muxes[pad].bank_ports[num].oe.eq(
- pads[pad][mux].oe)
- elif pin == "rx":
- comb += pads[pad][mux].eq(muxes[pad].bank_ports[num].i)
-
+ elif sig_type == iotypes['+']:
+ comb += muxes[pad].bank_ports[num].o.eq(pads[pad][mux])
+ elif sig_type == iotypes['-']:
+ comb += pads[pad][mux].eq(muxes[pad].bank_ports[num].i)
# ---------------------------
# Here is where the muxes are assigned to the actual pads
# ---------------------------
"""
def uart_send(tx, rx, pad_tx, pad_rx, byte, delay=1e-6):
# Drive uart tx - check the word seen at the Pad
- yield tx.oe.eq(1)
- yield tx.o.eq(1)
+ print(type(tx))
+ #yield tx.oe.eq(1)
+ yield tx.eq(1)
yield Delay(2*delay)
- yield tx.o.eq(0) # start bit
+ yield tx.eq(0) # start bit
yield Delay(delay)
read = 0
# send one byte, lsb first
for i in range(0, 8):
bit = (byte >> i) & 0x1
- yield tx.o.eq(bit)
+ yield tx.eq(bit)
yield Delay(delay)
test_bit = yield pad_tx.o
read |= (test_bit << i)
- yield tx.o.eq(1) # stop bit
+ yield tx.eq(1) # stop bit
yield Delay(delay)
assert byte == read, f"UART Sent: %x | Pad Read: %x" % (byte, read)
# Drive Pad i - check word at uart rx
def sim_man_pinmux():
filename = "test_man_pinmux"
- requested = {"N1": {"mux%d" % GPIO_BANK: ["gpio", 0],
- "mux%d" % UART_BANK: ["uart", 0, "tx"],
- "mux%d" % I2C_BANK: ["i2c", 0, "sda"]},
- "N2": {"mux%d" % GPIO_BANK: ["gpio", 1],
- "mux%d" % UART_BANK: ["uart", 0, "rx"],
- "mux%d" % I2C_BANK: ["i2c", 0, "scl"]},
- "N3": {"mux%d" % GPIO_BANK: ["gpio", 2]},
- "N4": {"mux%d" % GPIO_BANK: ["gpio", 3]}
+ requested = {"N1": {"mux%d" % GPIO_BANK: ["gpio", 0, '0*'],
+ "mux%d" % UART_BANK: ["uart", 0, 'tx+'],
+ "mux%d" % I2C_BANK: ["i2c", 0, 'sda*']},
+ "N2": {"mux%d" % GPIO_BANK: ["gpio", 1, '*'],
+ "mux%d" % UART_BANK: ["uart", 0, 'rx-'],
+ "mux%d" % I2C_BANK: ["i2c", 0, 'scl*']},
+ "N3": {"mux%d" % GPIO_BANK: ["gpio", 2, '0*']},
+ "N4": {"mux%d" % GPIO_BANK: ["gpio", 3, '0*']}
}
dut = ManPinmux(requested)
vl = rtlil.convert(dut, ports=dut.ports())
if __name__ == '__main__':
sim_man_pinmux()
+ #pinbanks = []
+ #fixedpins = []
+ #function_names = []
+ #testspec = PinSpec()
+ pinbanks = {
+ 'A': (4, 4), # (num of pads, num of banks)?
+ #'B': (18, 4),
+ #'C': (24, 1),
+ #'D': (93, 1),
+ }
+ fixedpins = {
+ 'POWER_GPIO': [
+ 'VDD_GPIOB',
+ 'GND_GPIOB',
+ ]}
+ function_names = {'TWI0': 'I2C 0',
+ 'UART0': 'UART (TX/RX) 0',
+ }
+ ps = PinSpec(pinbanks, fixedpins, function_names)
+ # Unit number, (Bank, pin #), mux, start, num # pins
+ ps.gpio("", ('A', 0), 0, 0, 4)
+ ps.uart("0", ('A', 0), 1)
+ ps.i2c("0", ('A', 0), 2)
+
+ print(dir(ps.gpio))
+ #print(ps.gpio.pinouts, ps.gpio.bankspec, ps.gpio.pinfn, ps.gpio.fname)
+ """
+ desc_dict_keys = ['UART0', 'TWI0', 'GPIOA_A0', 'GPIOA_A1', 'GPIOA_A2', 'GPIOA_A3']
+ eint = []
+ pwm = []
+ desc = {'UART0': 'Basic serial TX/RX serial port',
+ 'TWI0': 'I2C interface',
+ 'GPIOA_A0': 'Test GPIO0',
+ 'GPIOA_A1': 'Test GPIO1',
+ 'GPIOA_A2': 'Test GPIO2',
+ 'GPIOA_A3': 'Test GPIO3'}
+ ps.add_scenario("Test Manual Pinmux", desc_dict_keys, eint, pwm, desc)
+ """
+ print("---------------------------------")
+ #with open("test.mdwn", "w") as of:
+ # pinout, bankspec, pin_spec, fixedpins = ps.write(of)
+ #print("---------------------------------")
+
+ bk = ps.pinbanks.keys()
+ for bank in bk:
+ muxwidth = ps.muxwidths[bank]
+ print(bank, muxwidth)
+ pinidx = sorted(ps.keys())
+ for pin in pinidx:
+ print("---------------------------------")
+ print(pin)
+ pdata = ps.get(pin)
+ for mux in range(muxwidth):
+ if mux not in pdata:
+ print("Mux %d : NC" % mux)
+ else:
+ name, assigned_bank = pdata[mux]
+ print("Mux %d : %s" % (mux, name))
+
+
+
projects / pinmux.git / blobdiff