print("Test Manual Pinmux!")
self.gen_pinmux_dict(ps)
+ self.pads = {}
+
+ print("--------------------")
# Automatically create the necessary periph/pad Records/Signals
# depending on the given dict specification
for pad in self.requested.keys():
self.pads[pad] = {}
self.pads[pad]["pad"] = Record(name=pad, layout=io_layout)
- self.muxes[pad] = IOMuxBlockSingle(self.n_ports)
+ self.pads[pad]["n_ports"] = len(self.requested[pad])
+ if self.pads[pad]["n_ports"] == 1:
+ pass # skip mux creation
+ else:
+ print(self.pads[pad]["n_ports"])
+ # Need to determine num of bits - to make number a pow of 2
+ portsize = self.pads[pad]["n_ports"].bit_length()
+ self.pads[pad]["port"] = Signal(portsize, name="%s_port" % (pad))
+ self.muxes[pad] = IOMuxBlockSingle(self.pads[pad]["n_ports"])
for mux in self.requested[pad].keys():
periph = self.requested[pad][mux]["periph"]
suffix = self.requested[pad][mux]["suffix"]
m = Module()
comb, sync = m.d.comb, m.d.sync
muxes = self.muxes
- port = self.port
pads = self.pads
for pad in pads.keys():
- m.submodules[pad+"_mux"] = muxes[pad]
- # all muxes controlled by the same multi-bit signal
- comb += muxes[pad].port.eq(port)
+ if len(self.requested[pad]) == 1:
+ pass
+ else:
+ port = self.pads[pad]["port"]
+ m.submodules[pad+"_mux"] = muxes[pad]
+ # TODO: all muxes controlled by the same multi-bit signal
+ comb += muxes[pad].port.eq(port)
# print(self.requested)
# print(self.pads)
# This section connects the periphs to the assigned ports
# ---------------------------
for pad in pads.keys():
- for mux in self.requested[pad].keys():
+ if len(self.requested[pad]) == 1:
+ # connect directly
+ mux = 0 # assume only port0 has been defined
+ print(self.requested[pad])
periph = self.requested[pad][mux]["periph"]
#suffix = self.requested[pad][mux]["suffix"]
sig = self.requested[pad][mux]["signal"][:-1]
sig_type = iotypes[self.requested[pad][mux]["signal"][-1]]
- num = int(mux)
if sig_type == iotypes['*']:
- comb += muxes[pad].periph_ports[num].o.eq(pads[pad][mux].o)
- comb += muxes[pad].periph_ports[num].oe.eq(
- pads[pad][mux].oe)
- comb += pads[pad][mux].i.eq(muxes[pad].periph_ports[num].i)
+ comb += pads[pad]["pad"].o.eq(pads[pad][mux].o)
+ comb += pads[pad]["pad"].oe.eq(pads[pad][mux].oe)
+ comb += pads[pad][mux].i.eq(pads[pad]["pad"].i)
elif sig_type == iotypes['+']:
- comb += muxes[pad].periph_ports[num].o.eq(pads[pad][mux])
+ comb += pads[pad]["pad"].o.eq(pads[pad][mux].o)
elif sig_type == iotypes['-']:
- comb += pads[pad][mux].eq(muxes[pad].periph_ports[num].i)
+ comb += pads[pad][mux].i.eq(pads[pad]["pad"].i)
+ else:
+ for mux in self.requested[pad].keys():
+ periph = self.requested[pad][mux]["periph"]
+ #suffix = self.requested[pad][mux]["suffix"]
+ sig = self.requested[pad][mux]["signal"][:-1]
+ sig_type = iotypes[self.requested[pad][mux]["signal"][-1]]
+ num = int(mux)
+ print(pad, mux, sig, sig_type)
+ print(len(muxes[pad].periph_ports))
+ if sig_type == iotypes['*']:
+ comb += muxes[pad].periph_ports[num].o.eq(
+ pads[pad][mux].o)
+ comb += muxes[pad].periph_ports[num].oe.eq(
+ pads[pad][mux].oe)
+ comb += pads[pad][mux].i.eq(
+ muxes[pad].periph_ports[num].i)
+ elif sig_type == iotypes['+']:
+ comb += muxes[pad].periph_ports[num].o.eq(
+ pads[pad][mux])
+ elif sig_type == iotypes['-']:
+ comb += pads[pad][mux].eq(
+ muxes[pad].periph_ports[num].i)
# ---------------------------
# Here is where the muxes are assigned to the actual pads
# ---------------------------
for pad in pads.keys():
- comb += pads[pad]["pad"].o.eq(muxes[pad].out_port.o)
- comb += pads[pad]["pad"].oe.eq(muxes[pad].out_port.oe)
- comb += muxes[pad].out_port.i.eq(pads[pad]["pad"].i)
+ if len(self.requested[pad]) == 1:
+ pass # if only one periph, no mux present
+ else:
+ comb += pads[pad]["pad"].o.eq(muxes[pad].out_port.o)
+ comb += pads[pad]["pad"].oe.eq(muxes[pad].out_port.oe)
+ comb += muxes[pad].out_port.i.eq(pads[pad]["pad"].i)
return m
def __iter__(self):
+ print("=============")
+ print(self.pads)
+ print("=============")
for pad in list(self.pads.keys()):
for field in self.pads[pad]["pad"].fields.values():
yield field
for mux in self.pads[pad].keys():
+ print(type(self.pads[pad][mux]))
+ print(pad, mux, self.pads[pad][mux])
if type(self.pads[pad][mux]) == Signal:
yield self.pads[pad][mux]
- else:
+ elif type(self.pads[pad][mux]) == Record:
for field in self.pads[pad][mux].fields.values():
yield field
- yield self.port
+ else:
+ print("%s is a var, not Sig/Rec, skipping!" % mux)
def ports(self):
return list(self)
- def gen_pinmux_dict(self, ps):
- #print("---------------------------------")
- #with open("test.mdwn", "w") as of:
- # pinout, bankspec, pin_spec, fixedpins = ps.write(of)
- #print("---------------------------------")
+ def gen_pinmux_dict(self, ps, write_file=False):
+ if write_file:
+ with open("test.mdwn", "w") as of:
+ pinout, bankspec, pin_spec, fixedpins = ps.write(of)
#print(ps.items())
#print(ps.byspec)
#print(ps.fnspec)
# TODO: get from ps
self.requested = {}
- self.n_ports = 4
- self.port = Signal(log2_int(self.n_ports))
- self.pads = {}
self.muxes = {}
# Create local list of peripheral names defined in pinfunctions.py
"signal":signal}
print(self.requested)
-def set_port(dut, port, delay=1e-6):
- yield dut.port.eq(port)
- yield Delay(delay)
+def set_port(dut, pad, port, delay=1e-6):
+ if dut.pads[pad]["n_ports"] == 1:
+ print("Pad %s only has one function, skipping setting mux!" % pad)
+ else:
+ yield dut.pads[pad]["port"].eq(port)
+ yield Delay(delay)
"""
GPIO test function
gpio_port = gpio_periph["mux"]
gp = dut.pads[padname][gpio_port]
pad = dut.pads[padname]["pad"]
- yield from set_port(dut, gpio_port)
+ yield from set_port(dut, padname, gpio_port)
yield from gpio(gp, pad, 0x5a5)
# UART test
for suffix in uarts.keys():
txpadname = uarts[suffix]["txpadname"]
rxpadname = uarts[suffix]["rxpadname"]
- uart_port = uarts[suffix]["txmux"] # TODO: Assuming same mux setting
- tx = dut.pads[txpadname][uart_port]
- rx = dut.pads[rxpadname][uart_port]
+ txport = uarts[suffix]["txmux"]
+ rxport = uarts[suffix]["rxmux"]
+ tx = dut.pads[txpadname][txport]
+ rx = dut.pads[rxpadname][rxport]
txpad = dut.pads[txpadname]["pad"]
rxpad = dut.pads[rxpadname]["pad"]
- yield from set_port(dut, UART_MUX)
+ yield from set_port(dut, txpadname, txport)
+ yield from set_port(dut, rxpadname, rxport)
yield from uart_send(tx, rx, txpad, rxpad, 0x42)
# I2C test
for suffix in i2cs.keys():
sdapadname = i2cs[suffix]["sdapadname"]
sclpadname = i2cs[suffix]["sclpadname"]
- i2c_port = i2cs[suffix]["sdamux"] # TODO: Assuming same mux setting
- sda = dut.pads[sdapadname][i2c_port]
- scl = dut.pads[sclpadname][i2c_port]
+ sdaport = i2cs[suffix]["sdamux"]
+ sclport = i2cs[suffix]["sclmux"]
+ sda = dut.pads[sdapadname][sdaport]
+ scl = dut.pads[sclpadname][sclport]
sdapad = dut.pads[sdapadname]["pad"]
-
- yield from set_port(dut, I2C_MUX)
- yield from i2c_send(sda, scl, sdapad, 0x67)
+ yield from set_port(dut, sdapadname, sdaport)
+ yield from set_port(dut, sclpadname, sclport)
+ yield from i2c_send(sda, scl, sdapad, 0x67)
def gen_gtkw_doc(module_name, requested, filename):
# GTKWave doc generation
temp_traces[1].append(('%s__i' % pad, 'in'))
temp_traces[1].append(('%s__o' % pad, 'out'))
temp_traces[1].append(('%s__oe' % pad, 'out'))
+ # Port signal
+ temp_traces[1].append(('%s_port[%d:0]'
+ % (pad, (n_ports-1).bit_length()-1), 'in'))
+
+ traces.append(temp_traces)
+ temp_traces = ("Pad %s Peripherals" % pad, [])
for mux in requested[pad].keys():
periph = requested[pad][mux]["periph"]
suffix = requested[pad][mux]["suffix"]
# TODO: cleanup
pin = requested[pad][mux]["signal"][:-1]
- if periph == "gpio":
- temp_traces[1].append(('gp%d__i' % suffix, 'in'))
- temp_traces[1].append(('gp%d__o' % suffix, 'out'))
- temp_traces[1].append(('gp%d__oe' % suffix, 'out'))
- elif periph == "uart":
- if pin == "tx":
- temp_traces[1].append(('tx%d__o' % suffix, 'out'))
- temp_traces[1].append(('tx%d__oe' % suffix, 'out'))
- pass
- elif pin == "rx":
- temp_traces[1].append(('rx%d' % suffix, 'in'))
- pass
- elif periph == "i2c":
- temp_traces[1].append(('%s%d__i' % (pin, suffix), 'in'))
- temp_traces[1].append(('%s%d__o' % (pin, suffix), 'out'))
- temp_traces[1].append(('%s%d__oe' % (pin, suffix), 'out'))
+ sig_type = iotypes[requested[pad][mux]["signal"][-1]]
+ #print(sig, sig_type)
+ if periph == "GPIO":
+ name_format = "%s%s" % (pin, suffix)
+ else:
+ name_format = "%s%s" % (pin, suffix)
+ if sig_type == iotypes['*']:
+ temp_traces[1].append(('%s__i' % name_format, 'in'))
+ temp_traces[1].append(('%s__o' % name_format, 'out'))
+ temp_traces[1].append(('%s__oe' % name_format, 'out'))
+ # Single underscore because Signal, not Record
+ if sig_type == iotypes['+']:
+ temp_traces[1].append(('%s_o' % name_format, 'out'))
+ if sig_type == iotypes['-']:
+ temp_traces[1].append(('%s_i' % name_format, 'in'))
traces.append(temp_traces)
- # master port signal
- temp_traces = ('Misc', [
- ('port[%d:0]' % ((n_ports-1).bit_length()-1), 'in')
- ])
- traces.append(temp_traces)
-
#print(traces)
write_gtkw(filename+".gtkw", filename+".vcd", traces, style,