update README

[libresoc-litex.git] / versa_ecp5.py

diff --git a/versa_ecp5.py b/versa_ecp5.py
index 18aca0eedf6f9f8ab3ecffa5fd6e98d305e92376..42ff88f24b2bf4c7d766547f4c83439508a31f32 100755 (executable)
--- a/versa_ecp5.py
+++ b/versa_ecp5.py
@@ -2,9 +2,14 @@
 
 import os
 import argparse
+import sys
 
 import litex_boards.targets.versa_ecp5 as versa_ecp5
 import litex_boards.targets.ulx3s as ulx3s
+#import litex_boards.targets.arty as arty
+import digilent_arty as arty
+
+from litex.build.lattice.trellis import trellis_args, trellis_argdict
 
 from litex.soc.integration.soc_sdram import (soc_sdram_args,
                                              soc_sdram_argdict)
@@ -12,7 +17,7 @@ from litex.soc.integration.builder import (Builder, builder_args,
                                            builder_argdict)
 
 from libresoc import LibreSoC
-#from microwatt import Microwatt
+from microwatt import Microwatt
 
 # HACK!
 from litex.soc.integration.soc import SoCCSRHandler
@@ -29,7 +34,7 @@ class VersaECP5TestSoC(versa_ecp5.BaseSoC):
         kwargs["integrated_rom_size"] = 0x10000
         #kwargs["integrated_main_ram_size"] = 0x1000
         kwargs["csr_data_width"] = 32
-        kwargs['csr_address_width'] = 12 # limit to 0x8000
+        kwargs['csr_address_width'] = 15 # limit to 0x8000
         kwargs["l2_size"] = 0
         #bus_data_width = 16,
 
@@ -79,6 +84,7 @@ class ULX3S85FTestSoC(ulx3s.BaseSoC):
         kwargs["integrated_rom_size"] = 0x10000
         #kwargs["integrated_main_ram_size"] = 0x1000
         kwargs["csr_data_width"] = 32
+        kwargs['csr_address_width'] = 15 # limit to 0x8000
         kwargs["l2_size"] = 0
         #bus_data_width = 16,
 
@@ -108,6 +114,27 @@ class ULX3S85FTestSoC(ulx3s.BaseSoC):
         self.comb += self.cpu.jtag_tdi.eq(jtag_tdi)
         self.comb += jtag_tdo.eq(self.cpu.jtag_tdo)
 
+
+class ArtyTestSoC(arty.BaseSoC):
+    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
+        kwargs["integrated_rom_size"] = 0x10000
+        #kwargs["integrated_main_ram_size"] = 0x1000
+        kwargs["csr_data_width"] = 32
+        kwargs['csr_address_width'] = 15 # limit to 0x8000
+        kwargs["l2_size"] = 0
+        #bus_data_width = 16,
+
+        arty.BaseSoC.__init__(self,
+            sys_clk_freq = sys_clk_freq,
+            cpu_type     = "external",
+            cpu_cls      = LibreSoC,
+            cpu_variant  = "standardjtag",
+            #cpu_cls      = Microwatt,
+            variant      = "a7-100",
+            toolchain    = "symbiflow",
+            **kwargs)
+
+
 # Build
 # ----------------------------------------------------------------------------
 
@@ -120,11 +147,15 @@ def main():
                         help="System clock frequency (default=16MHz)")
     parser.add_argument("--fpga", default="versa_ecp5", help="FPGA target " \
                         "to build for/load to")
+    parser.add_argument("--load-from", default=None, help="svf to load, disables build")
+    parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
 
     builder_args(parser)
     soc_sdram_args(parser)
+    trellis_args(parser)
     args = parser.parse_args()
 
+    loadext = ".svf"
     if args.fpga == "versa_ecp5":
         soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
                                **soc_sdram_argdict(args))
@@ -133,17 +164,32 @@ def main():
         soc = ULX3S85FTestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
                               **soc_sdram_argdict(args))
 
+    elif args.fpga == "artya7100t":
+        soc = ArtyTestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
+                              **soc_sdram_argdict(args))
+        loadext = ".bit"
+
     else:
         soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
                                **soc_sdram_argdict(args))
 
-    builder = Builder(soc, **builder_argdict(args))
-    builder.build(run=args.build)
+    if args.load_from == None:
+        builder = Builder(soc, **builder_argdict(args))
+        builder_kargs = trellis_argdict(args) \
+                if args.toolchain == "trellis" else {}
+        builder.build(**builder_kargs, run=args.build)
 
-    if args.load:
+        if args.load:
+            prog = soc.platform.create_programmer()
+            prog.load_bitstream(os.path.join(builder.gateware_dir,
+                                           soc.build_name + loadext))
+    else:
+        if args.load or args.build:
+            print("--load-from is incompatible with --load and --build",
+                  file=sys.stderr)
+            sys.exit(1)
         prog = soc.platform.create_programmer()
-        prog.load_bitstream(os.path.join(builder.gateware_dir,
-                                         soc.build_name + ".svf"))
+        prog.load_bitstream(args.load_from)
 
 if __name__ == "__main__":
     main()