update README

[libresoc-litex.git] / versa_ecp5.py

diff --git a/versa_ecp5.py b/versa_ecp5.py
index 4b6b1284dda4a571b2d178ccb0ccff39b0dcf859..42ff88f24b2bf4c7d766547f4c83439508a31f32 100755 (executable)
--- a/versa_ecp5.py
+++ b/versa_ecp5.py
@@ -17,7 +17,7 @@ from litex.soc.integration.builder import (Builder, builder_args,
                                            builder_argdict)
 
 from libresoc import LibreSoC
-#from microwatt import Microwatt
+from microwatt import Microwatt
 
 # HACK!
 from litex.soc.integration.soc import SoCCSRHandler
@@ -84,6 +84,7 @@ class ULX3S85FTestSoC(ulx3s.BaseSoC):
         kwargs["integrated_rom_size"] = 0x10000
         #kwargs["integrated_main_ram_size"] = 0x1000
         kwargs["csr_data_width"] = 32
+        kwargs['csr_address_width'] = 15 # limit to 0x8000
         kwargs["l2_size"] = 0
         #bus_data_width = 16,
 
@@ -151,21 +152,22 @@ def main():
 
     builder_args(parser)
     soc_sdram_args(parser)
+    trellis_args(parser)
     args = parser.parse_args()
 
+    loadext = ".svf"
     if args.fpga == "versa_ecp5":
-        trellis_args(parser)
         soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
                                **soc_sdram_argdict(args))
 
     elif args.fpga == "ulx3s85f":
-        trellis_args(parser)
         soc = ULX3S85FTestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
                               **soc_sdram_argdict(args))
 
     elif args.fpga == "artya7100t":
         soc = ArtyTestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
                               **soc_sdram_argdict(args))
+        loadext = ".bit"
 
     else:
         soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
@@ -180,10 +182,11 @@ def main():
         if args.load:
             prog = soc.platform.create_programmer()
             prog.load_bitstream(os.path.join(builder.gateware_dir,
-                                           soc.build_name + ".svf"))
+                                           soc.build_name + loadext))
     else:
         if args.load or args.build:
-            print("--load-from is incompatible with --load and --build", file=sys.stderr)
+            print("--load-from is incompatible with --load and --build",
+                  file=sys.stderr)
             sys.exit(1)
         prog = soc.platform.create_programmer()
         prog.load_bitstream(args.load_from)