X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=src%2Fmain%2Fscala%2Fdevices%2Fuart%2FUART.scala;h=449f897819a57427a8a8e978569df70745bebe2b;hb=4fcf349adb9e66ea7d8cc5394de5d3e0a2340985;hp=de2cf554a33c1a4d061317b5f182619cee25fe98;hpb=fe65a87c5c94466ce17896cfd896c8e7c127d79b;p=sifive-blocks.git

diff --git a/src/main/scala/devices/uart/UART.scala b/src/main/scala/devices/uart/UART.scala
index de2cf55..449f897 100644
--- a/src/main/scala/devices/uart/UART.scala
+++ b/src/main/scala/devices/uart/UART.scala
@@ -2,6 +2,7 @@
 package sifive.blocks.devices.uart
 
 import Chisel._
+import chisel3.experimental.MultiIOModule
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.tilelink._
@@ -198,7 +199,7 @@ class UARTInterrupts extends Bundle {
   val txwm = Bool()
 }
 
-trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasRegMap {
+trait HasUARTTopModuleContents extends MultiIOModule with HasUARTParameters with HasRegMap {
   val io: HasUARTTopBundleContents
   implicit val p: Parameters
   def params: UARTParams