X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=README.md;h=850878a8bd7abd71e8f61fc4a7defabd69e05166;hb=45351b73c557e587b6eaf574074535d73cd6b56b;hp=9a4e91370c960b7c59262009186b2e5428f4ade8;hpb=0169cffd9364d2c70d556cc8ad3c083c79c8aeb1;p=riscv-tests.git

diff --git a/README.md b/README.md
index 9a4e913..850878a 100644
--- a/README.md
+++ b/README.md
@@ -10,9 +10,9 @@ Building from repository
 -----------------------------
 
 We assume that the RISCV environment variable is set to the RISC-V tools
-install path, and that the riscv-gcc package is installed.
+install path, and that the riscv-gnu-toolchain package is installed.
 
-    $ git clone https://github.com/ucb-bar/riscv-tests
+    $ git clone https://github.com/riscv/riscv-tests
     $ cd riscv-tests
     $ git submodule update --init --recursive
     $ autoconf
@@ -134,7 +134,7 @@ registers (pc, x0-x31, f0-f31, fsr) can be accessed.
 The `rv32ui` and `rv64ui` TVMs are integer-only subsets of `rv32u` and `rv64u`
 respectively. These subsets can not use any floating-point instructions (major
 opcodes: LOAD-FP, STORE-FP, MADD, MSUB, NMSUB, NMADD, OP-FP), and hence cannot
-access the floating-point register state (f0â-f31 and fsr). The integer-only
+access the floating-point register state (f0-f31 and fsr). The integer-only
 TVMs are useful for initial processor bringup and to test simpler
 implementations that lack a hardware FPU.