X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=TLB%2Fsrc%2FRegisterFile.py;h=317d240f004f2a18419d7597e36d37d09a951ce8;hb=a7701acbb1b133dd4e377b6dd6096d763d174eb2;hp=5fd691c8db81624115eabf148b751b5787c7cf1e;hpb=7659f4bdf55f544280ea938739310f5446888531;p=soc.git

diff --git a/TLB/src/RegisterFile.py b/TLB/src/RegisterFile.py
index 5fd691c8..317d240f 100644
--- a/TLB/src/RegisterFile.py
+++ b/TLB/src/RegisterFile.py
@@ -3,38 +3,38 @@ from nmigen.lib.coding import Decoder
 
 class RegisterFile():
     """ Register File
-        
+
         The purpose of this module is to represent a bank of registers.
-        
+
         Usage:
         To Write: Set the address line to the desired register in the file, set
         write_enable HIGH, and wait one cycle
         To Read: Set the address line to the desired register in the file, set
-        write_enable LOW, and wait one cycle. 
+        write_enable LOW, and wait one cycle.
     """
-    
+
     def __init__(self, data_size, file_size):
         """ Arguments:
             * data_size: (bit count) The number of bits in one register
             * cam_size: (entry count) the number of registers in this file
         """
-        
+
         # Internal
         self.register_array = Array(Signal(data_size) for x in range(file_size))
-        
+
         # Input
         self.enable = Signal(1)
         self.write_enable = Signal(1)
         self.address = Signal(max=file_size)
         self.data_i = Signal(data_size)
-        
+
         # Output
         self.valid = Signal(1)
         self.data_o = Signal(data_size)
-        
+
     def elaborate(self, platform=None):
         m = Module()
-        
+
         with m.If(self.enable):
             # Write Logic
             with m.If(self.write_enable):
@@ -54,6 +54,6 @@ class RegisterFile():
             m.d.sync += [
                 self.valid.eq(0),
                 self.data_o.eq(0)
-            ]            
-        
-        return m
\ No newline at end of file
+            ]
+
+        return m