X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=debug%2Ftargets%2FRISC-V%2Fspike-rtos.cfg;h=e26ca8a43c4d8b37141ff05158fb8bc0239e5b2f;hb=4dddbc79ada7f0a836cf538676c57c8df103ccf6;hp=159a70fac42c7ffcaa6af1f1371ef43f0f73fdce;hpb=45380af7d42ee3302fc229030694f8ea4506d79f;p=riscv-tests.git

diff --git a/debug/targets/RISC-V/spike-rtos.cfg b/debug/targets/RISC-V/spike-rtos.cfg
index 159a70f..e26ca8a 100644
--- a/debug/targets/RISC-V/spike-rtos.cfg
+++ b/debug/targets/RISC-V/spike-rtos.cfg
@@ -12,10 +12,12 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
 
 gdb_report_data_abort enable
+gdb_report_register_access_error enable
 
 # Expose an unimplemented CSR so we can test non-existent register access
 # behavior.
 riscv expose_csrs 2288
+riscv expose_custom 1,12345-12348
 
 init