X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=debug%2Ftargets%2FRISC-V%2Fspike32-2.py;h=89d3c2a3602bbc59bd96f92bdeda052df81d167d;hb=fc3d7e8196dfb567a9b6c34dd97c1b43260b4cd5;hp=09bab1d05017289233d626f0d4cc341dde2d8256;hpb=28fbcac967d6c2a0085faa2007c98d64d3203491;p=riscv-tests.git

diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py
index 09bab1d..89d3c2a 100644
--- a/debug/targets/RISC-V/spike32-2.py
+++ b/debug/targets/RISC-V/spike32-2.py
@@ -5,7 +5,8 @@ import spike32  # pylint: disable=import-error
 
 class spike32_2(targets.Target):
     harts = [spike32.spike32_hart(), spike32.spike32_hart()]
-    openocd_config_path = "spike.cfg"
+    openocd_config_path = "spike-2.cfg"
+    timeout_sec = 30
 
     def create(self):
-        return testlib.Spike(self)
+        return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0)