X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=debug%2Ftargets%2FRISC-V%2Fspike32-2.py;h=f57f816afeedaff230cb07aec4507a17c42ca733;hb=d359b6252eceb5e28f1048591750954d09efd12b;hp=6cf558d4b936c6634100ecde00d289990b50129c;hpb=6650f4e3f7b11d581a8be07a2beb16f69530fb36;p=riscv-tests.git

diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py
index 6cf558d..f57f816 100644
--- a/debug/targets/RISC-V/spike32-2.py
+++ b/debug/targets/RISC-V/spike32-2.py
@@ -5,8 +5,8 @@ import spike32  # pylint: disable=import-error
 
 class spike32_2(targets.Target):
     harts = [spike32.spike32_hart(), spike32.spike32_hart()]
-    openocd_config_path = "spike.cfg"
+    openocd_config_path = "spike-2.cfg"
     timeout_sec = 30
 
     def create(self):
-        return testlib.Spike(self)
+        return testlib.Spike(self, isa="RV32IMAFC")