X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=debug%2Ftargets%2FRISC-V%2Fspike32.py;h=dfcfc0134dc26a67dedbc1ee79fd4e0d3d1c38c2;hb=d359b6252eceb5e28f1048591750954d09efd12b;hp=3bf8b4783c4578bb5f671b9036c5a08de37c7ab4;hpb=272e12eb177c662826f901d536f685a4abf62123;p=riscv-tests.git

diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py
index 3bf8b47..dfcfc01 100644
--- a/debug/targets/RISC-V/spike32.py
+++ b/debug/targets/RISC-V/spike32.py
@@ -1,12 +1,19 @@
 import targets
 import testlib
 
-class spike32(targets.Target):
+class spike32_hart(targets.Hart):
     xlen = 32
     ram = 0x10000000
     ram_size = 0x10000000
     instruction_hardware_breakpoint_count = 4
-    reset_vector = 0x1000
+    reset_vectors = [0x1000]
+    link_script_path = "spike32.lds"
+
+class spike32(targets.Target):
+    harts = [spike32_hart()]
+    openocd_config_path = "spike-1.cfg"
+    timeout_sec = 30
 
     def create(self):
-        return testlib.Spike(self)
+        # 64-bit FPRs on 32-bit target
+        return testlib.Spike(self, isa="RV32IMAFDC")