X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=debug%2Ftargets%2FRISC-V%2Fspike64.py;h=2aa1dd057ef66a9723f76c201763658604b3b409;hb=d359b6252eceb5e28f1048591750954d09efd12b;hp=6e3da896ef01b79a454893fe964def2da1c441ab;hpb=6650f4e3f7b11d581a8be07a2beb16f69530fb36;p=riscv-tests.git

diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py
index 6e3da89..2aa1dd0 100644
--- a/debug/targets/RISC-V/spike64.py
+++ b/debug/targets/RISC-V/spike64.py
@@ -6,13 +6,14 @@ class spike64_hart(targets.Hart):
     ram = 0x1212340000
     ram_size = 0x10000000
     instruction_hardware_breakpoint_count = 4
-    reset_vector = 0x1000
+    reset_vectors = [0x1000]
     link_script_path = "spike64.lds"
 
 class spike64(targets.Target):
     harts = [spike64_hart()]
-    openocd_config_path = "spike.cfg"
+    openocd_config_path = "spike-1.cfg"
     timeout_sec = 30
 
     def create(self):
-        return testlib.Spike(self)
+        # 32-bit FPRs only
+        return testlib.Spike(self, isa="RV64IMAFC")