X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Fexample_buf_pipe.py;h=037d35db30070c4d0133ff1358f7bbd40863ee70;hb=64bd11bded25d7262bc98c40aa609c275eded4b2;hp=568c7c692b901c69ef592708fa1d7f57bed2a052;hpb=e9ce8cefa80c97dc9dc027edb436b5ca97ae9d9f;p=ieee754fpu.git diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py index 568c7c69..037d35db 100644 --- a/src/add/example_buf_pipe.py +++ b/src/add/example_buf_pipe.py @@ -65,7 +65,7 @@ class PrevControl: """ return [self.i_valid.eq(prev.i_valid), prev.o_ready.eq(self.o_ready), - eq(self.data, prev.data), + eq(self.i_data, prev.i_data), ] @@ -85,7 +85,7 @@ class NextControl: """ return [nxt.i_valid.eq(self.o_valid), self.i_ready.eq(nxt.o_ready), - eq(nxt.data, self.data), + eq(nxt.i_data, self.o_data), ] def connect_out(self, nxt): @@ -94,11 +94,15 @@ class NextControl: """ return [nxt.o_valid.eq(self.o_valid), self.i_ready.eq(nxt.i_ready), - eq(nxt.data, self.data), + eq(nxt.o_data, self.o_data), ] def eq(o, i): + """ makes signals equal: a helper routine which identifies if it is being + passsed a list (or tuple) of objects, and calls the objects' eq + function. + """ if not isinstance(o, Sequence): o, i = [o], [i] res = [] @@ -107,32 +111,8 @@ def eq(o, i): return res -class BufferedPipeline: - """ buffered pipeline stage. data and strobe signals travel in sync. - if ever the input is ready and the output is not, processed data - is stored in a temporary register. - - stage-1 p.i_valid >>in stage n.o_valid out>> stage+1 - stage-1 p.o_ready <>in stage n.data out>> stage+1 - | | - process --->----^ - | | - +-- r_data ->-+ - - input data p.data is read (only), is processed and goes into an - intermediate result store [process()]. this is updated combinatorially. - - in a non-stall condition, the intermediate result will go into the - output (update_output). however if ever there is a stall, it goes - into r_data instead [update_buffer()]. - - when the non-stall condition is released, r_data is the first - to be transferred to the output [flush_buffer()], and the stall - condition cleared. - - on the next cycle (as long as stall is not raised again) the - input may begin to be processed and transferred directly to output. +class PipelineBase: + """ Common functions for Pipeline API """ def __init__(self, stage): """ pass in a "stage" which may be either a static class or a class @@ -141,10 +121,9 @@ class BufferedPipeline: * ispec: returns output signals to the output specification * process: takes an input instance and returns processed data - p.data -> process() -> result --> n.data - | ^ - | | - +-> r_data -+ + User must also: + * add i_data member to PrevControl and + * add o_data member to NextControl """ self.stage = stage @@ -152,12 +131,6 @@ class BufferedPipeline: self.p = PrevControl() self.n = NextControl() - # set up the input and output data - self.p.data = stage.ispec() # input type - self.r_data = stage.ospec() # all these are output type - self.result = stage.ospec() - self.n.data = stage.ospec() - def connect_to_next(self, nxt): """ helper function to connect to the next stage data/valid/ready. """ @@ -178,32 +151,56 @@ class BufferedPipeline: def set_input(self, i): """ helper function to set the input data """ - return eq(self.p.data, i) + return eq(self.p.i_data, i) - def update_buffer(self): - """ copies the result into the intermediate register r_data, - which will need to be outputted on a subsequent cycle - prior to allowing "normal" operation. - """ - return eq(self.r_data, self.result) + def ports(self): + return [self.p.i_valid, self.n.i_ready, + self.n.o_valid, self.p.o_ready, + self.p.i_data, self.n.o_data # XXX need flattening! + ] - def update_output(self): - """ copies the (combinatorial) result into the output - """ - return eq(self.n.data, self.result) - def flush_buffer(self): - """ copies the *intermediate* register r_data into the output - """ - return eq(self.n.data, self.r_data) +class BufferedPipeline(PipelineBase): + """ buffered pipeline stage. data and strobe signals travel in sync. + if ever the input is ready and the output is not, processed data + is stored in a temporary register. - def ports(self): - return [self.p.data, self.n.data] + stage-1 p.i_valid >>in stage n.o_valid out>> stage+1 + stage-1 p.o_ready <>in stage n.o_data out>> stage+1 + | | + process --->----^ + | | + +-- r_data ->-+ + + input data p.i_data is read (only), is processed and goes into an + intermediate result store [process()]. this is updated combinatorially. + + in a non-stall condition, the intermediate result will go into the + output (update_output). however if ever there is a stall, it goes + into r_data instead [update_buffer()]. + + when the non-stall condition is released, r_data is the first + to be transferred to the output [flush_buffer()], and the stall + condition cleared. + + on the next cycle (as long as stall is not raised again) the + input may begin to be processed and transferred directly to output. + """ + def __init__(self, stage): + PipelineBase.__init__(self, stage) + + # set up the input and output data + self.p.i_data = stage.ispec() # input type + self.n.o_data = stage.ospec() def elaborate(self, platform): m = Module() + + result = self.stage.ospec() + r_data = self.stage.ospec() if hasattr(self.stage, "setup"): - self.stage.setup(m, self.p.data) + self.stage.setup(m, self.p.i_data) # establish some combinatorial temporaries o_n_validn = Signal(reset_less=True) @@ -213,11 +210,11 @@ class BufferedPipeline: ] # store result of processing in combinatorial temporary - with m.If(self.p.i_valid): # input is valid: process it - m.d.comb += eq(self.result, self.stage.process(self.p.data)) + #with m.If(self.p.i_valid): # input is valid: process it + m.d.comb += eq(result, self.stage.process(self.p.i_data)) # if not in stall condition, update the temporary register with m.If(self.p.o_ready): # not stalled - m.d.sync += self.update_buffer() + m.d.sync += eq(r_data, result) # update buffer #with m.If(self.p.i_rst): # reset # m.d.sync += self.n.o_valid.eq(0) @@ -226,12 +223,12 @@ class BufferedPipeline: with m.If(self.p.o_ready): # not stalled # nothing in buffer: send (processed) input direct to output m.d.sync += [self.n.o_valid.eq(self.p.i_valid), - self.update_output(), + eq(self.n.o_data, result), # update output ] with m.Else(): # p.o_ready is false, and something is in buffer. # Flush the [already processed] buffer to the output port. m.d.sync += [self.n.o_valid.eq(1), - self.flush_buffer(), + eq(self.n.o_data, r_data), # flush buffer # clear stall condition, declare register empty. self.p.o_ready.eq(1), ] @@ -242,7 +239,7 @@ class BufferedPipeline: m.d.sync += [self.n.o_valid.eq(self.p.i_valid), self.p.o_ready.eq(1), # Keep the buffer empty # set the output data (from comb result) - self.update_output(), + eq(self.n.o_data, result), ] # (n.i_ready) false and (n.o_valid) true: with m.Elif(i_p_valid_o_p_ready): @@ -251,11 +248,6 @@ class BufferedPipeline: return m - def ports(self): - return [self.p.i_valid, self.n.i_ready, - self.n.o_valid, self.p.o_ready, - ] - class ExampleAddStage: """ an example of how to use the buffered pipeline, as a class instance @@ -312,7 +304,7 @@ class ExampleBufPipe(BufferedPipeline): BufferedPipeline.__init__(self, ExampleStage) -class CombPipe: +class CombPipe(PipelineBase): """A simple pipeline stage containing combinational logic that can execute completely in one clock cycle. @@ -338,41 +330,31 @@ class CombPipe: """ def __init__(self, stage): - self.stage = stage + PipelineBase.__init__(self, stage) self._data_valid = Signal() - # set up input and output IO ACK (prev/next ready/valid) - self.p = PrevControl() - self.n = NextControl() # set up the input and output data - self.p.data = stage.ispec() # input type - self.r_data = stage.ispec() # input type - self.result = stage.ospec() # output data - self.n.data = stage.ospec() # output type - self.n.data.name = "outdata" - - def set_input(self, i): - """ helper function to set the input data - """ - return eq(self.p.data, i) + self.p.i_data = stage.ispec() # input type + self.n.o_data = stage.ospec() # output type def elaborate(self, platform): m = Module() + + r_data = self.stage.ispec() # input type + result = self.stage.ospec() # output data if hasattr(self.stage, "setup"): - self.stage.setup(m, self.r_data) - m.d.comb += eq(self.result, self.stage.process(self.r_data)) + self.stage.setup(m, r_data) + + m.d.comb += eq(result, self.stage.process(r_data)) m.d.comb += self.n.o_valid.eq(self._data_valid) m.d.comb += self.p.o_ready.eq(~self._data_valid | self.n.i_ready) m.d.sync += self._data_valid.eq(self.p.i_valid | \ (~self.n.i_ready & self._data_valid)) with m.If(self.p.i_valid & self.p.o_ready): - m.d.sync += eq(self.r_data, self.p.data) - m.d.comb += eq(self.n.data, self.result) + m.d.sync += eq(r_data, self.p.i_data) + m.d.comb += eq(self.n.o_data, result) return m - def ports(self): - return [self.p.data, self.n.data] - class ExampleCombPipe(CombPipe): """ an example of how to use the combinatorial pipeline.