X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Fexample_buf_pipe.py;h=856fc7ab697ecf1ebbbb1dd726f6eb528f1a5613;hb=c3d0590519b298bebb9cb879eb884c6253749eca;hp=37cf38ba769977a1f3c639658d3c386f847a1842;hpb=47537cef175dc213da2bb76ddadbfd38d6bee619;p=ieee754fpu.git

diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py
index 37cf38ba..856fc7ab 100644
--- a/src/add/example_buf_pipe.py
+++ b/src/add/example_buf_pipe.py
@@ -110,25 +110,21 @@ class BufferedPipeline:
                                      |           |
                                      +-> r_data -+
         """
-        # input: strobe comes in from previous stage, ready comes in from next
-        self.i = IOAckIn()
-        #self.i.p_valid = Signal()    # >>in - comes in from PREVIOUS stage
-        #self.i.n_ready = Signal()   # in<< - comes in from the NEXT stage
+        self.stage = stage
 
-        # output: strobe goes out to next stage, ready comes in from previous
+        # set up input and output IO ACK (prev/next ready/valid)
+        self.i = IOAckIn()
         self.o = IOAckOut()
-        #self.o.n_valid = Signal()    # out>> - goes out to the NEXT stage
-        #self.o.p_ready = Signal()   # <<out - goes out to the PREVIOUS stage
 
         # set up the input and output data
         self.i.data = stage.ispec() # input type
         self.r_data = stage.ospec() # all these are output type
         self.result = stage.ospec()
         self.o.data = stage.ospec()
-        self.stage = stage
 
     def connect_next(self, nxt):
-        """ helper function to connect the next stage data/valid/ready
+        """ helper function to connect to the next stage data/valid/ready.
+            data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
         """
         return [nxt.i.p_valid.eq(self.o.n_valid),
                 self.i.n_ready.eq(nxt.o.p_ready),
@@ -288,8 +284,76 @@ class ExampleBufPipe(BufferedPipeline):
         BufferedPipeline.__init__(self, ExampleStage)
 
 
+class CombPipe:
+    """A simple pipeline stage containing combinational logic that can execute
+    completely in one clock cycle.
+
+    Parameters:
+    -----------
+    input_shape : int or tuple or None
+        the shape of ``input.data`` and ``comb_input``
+    output_shape : int or tuple or None
+        the shape of ``output.data`` and ``comb_output``
+    name : str
+        the name
+
+    Attributes:
+    -----------
+    input : StageInput
+        The pipeline input
+    output : StageOutput
+        The pipeline output
+    comb_input : Signal, input_shape
+        The input to the combinatorial logic
+    comb_output: Signal, output_shape
+        The output of the combinatorial logic
+    """
+
+    def __init__(self, stage):
+        self.stage = stage
+        self._data_valid = Signal()
+        # set up input and output IO ACK (prev/next ready/valid)
+        self.i = IOAckIn()
+        self.o = IOAckOut()
+
+        # set up the input and output data
+        self.i.data = stage.ispec() # input type
+        self.r_data = stage.ispec() # input type
+        self.o_comb = stage.ospec() # output data
+        self.o.data = stage.ospec() # output type
+        self.o.data.name = "outdata"
+
+    def elaborate(self, platform):
+        m = Module()
+        m.d.comb += eq(self.o_comb, self.stage.process(self.r_data))
+        m.d.comb += self.o.n_valid.eq(self._data_valid)
+        m.d.comb += self.o.p_ready.eq(~self._data_valid | self.i.n_ready)
+        m.d.sync += self._data_valid.eq(self.i.p_valid | \
+                                        (~self.i.n_ready & self._data_valid))
+        with m.If(self.i.p_valid & self.o.p_ready):
+            m.d.sync += eq(self.r_data, self.i.data)
+        m.d.comb += eq(self.o.data, self.o_comb)
+        return m
+
+    def ports(self):
+        return [self.i.data, self.o.data]
+
+
+class ExampleCombPipe(CombPipe):
+    """ an example of how to use the combinatorial pipeline.
+    """
+
+    def __init__(self):
+        CombPipe.__init__(self, ExampleStage)
+
+
 if __name__ == '__main__':
     dut = ExampleBufPipe()
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_bufpipe.il", "w") as f:
         f.write(vl)
+
+    dut = ExampleCombPipe()
+    vl = rtlil.convert(dut, ports=dut.ports())
+    with open("test_combpipe.il", "w") as f:
+        f.write(vl)