X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Fexample_buf_pipe.py;h=a1f5d04f565c1ec3cd1d2f813ca3fd9436fa6216;hb=749ea1efc895d5259e49062bd9025dd6b1051636;hp=15d368c291d5a737c1b73c5a53bfa82c00ce09bb;hpb=f201e4d673a3d15db93de5a6b79eceab6b89ba0d;p=ieee754fpu.git

diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py
index 15d368c2..a1f5d04f 100644
--- a/src/add/example_buf_pipe.py
+++ b/src/add/example_buf_pipe.py
@@ -45,6 +45,8 @@
 
 from nmigen import Signal, Cat, Const, Mux, Module
 from nmigen.cli import verilog, rtlil
+from nmigen.hdl.rec import Record, Layout
+
 from collections.abc import Sequence
 
 
@@ -56,8 +58,8 @@ class PrevControl:
     """
 
     def __init__(self):
-        self.i_valid = Signal(name="p_i_valid") # >>in
-        self.o_ready = Signal(name="p_o_ready") # <<out
+        self.i_valid = Signal(name="p_i_valid") # prev   >>in  self
+        self.o_ready = Signal(name="p_o_ready") # prev   <<out self
 
     def connect_in(self, prev):
         """ helper function to connect stage to an input source.  do not
@@ -76,8 +78,8 @@ class NextControl:
         * o_data : an output - added by the user of this class
     """
     def __init__(self):
-        self.o_valid = Signal(name="n_o_valid") # out>>
-        self.i_ready = Signal(name="n_i_ready") # <<in
+        self.o_valid = Signal(name="n_o_valid") # self out>>  next
+        self.i_ready = Signal(name="n_i_ready") # self <<in   next
 
     def connect_to_next(self, nxt):
         """ helper function to connect to the next stage data/valid/ready.
@@ -99,11 +101,29 @@ class NextControl:
 
 
 def eq(o, i):
+    """ makes signals equal: a helper routine which identifies if it is being
+        passsed a list (or tuple) of objects, and calls the objects' eq
+        function.
+
+        Record is a special (unusual, recursive) case, where the input
+        is specified as a dictionary (which may contain further dictionaries,
+        recursively), where the field names of the dictionary must match
+        the Record's field spec.
+    """
     if not isinstance(o, Sequence):
         o, i = [o], [i]
     res = []
     for (ao, ai) in zip(o, i):
-        res.append(ao.eq(ai))
+        #print ("eq", ao, ai)
+        if isinstance(ao, Record):
+            for idx, (field_name, field_shape, _) in enumerate(ao.layout):
+                if isinstance(field_shape, Layout):
+                    rres = eq(ao.fields[field_name], ai.fields[field_name])
+                else:
+                    rres = eq(ao.fields[field_name], ai[field_name])
+                res += rres
+        else:
+            res.append(ao.eq(ai))
     return res
 
 
@@ -152,7 +172,7 @@ class PipelineBase:
     def ports(self):
         return [self.p.i_valid, self.n.i_ready,
                 self.n.o_valid, self.p.o_ready,
-                self.p.i_data, self.n.o_data
+                self.p.i_data, self.n.o_data   # XXX need flattening!
                ]
 
 
@@ -188,29 +208,13 @@ class BufferedPipeline(PipelineBase):
 
         # set up the input and output data
         self.p.i_data = stage.ispec() # input type
-        self.r_data   = stage.ospec() # all these are output type
-        self.result   = stage.ospec()
         self.n.o_data = stage.ospec()
 
-    def update_buffer(self):
-        """ copies the result into the intermediate register r_data,
-            which will need to be outputted on a subsequent cycle
-            prior to allowing "normal" operation.
-        """
-        return eq(self.r_data, self.result)
-
-    def update_output(self):
-        """ copies the (combinatorial) result into the output
-        """
-        return eq(self.n.o_data, self.result)
-
-    def flush_buffer(self):
-        """ copies the *intermediate* register r_data into the output
-        """
-        return eq(self.n.o_data, self.r_data)
-
     def elaborate(self, platform):
         m = Module()
+
+        result = self.stage.ospec()
+        r_data = self.stage.ospec()
         if hasattr(self.stage, "setup"):
             self.stage.setup(m, self.p.i_data)
 
@@ -222,11 +226,11 @@ class BufferedPipeline(PipelineBase):
         ]
 
         # store result of processing in combinatorial temporary
-        with m.If(self.p.i_valid): # input is valid: process it
-            m.d.comb += eq(self.result, self.stage.process(self.p.i_data))
+        #with m.If(self.p.i_valid): # input is valid: process it
+        m.d.comb += eq(result, self.stage.process(self.p.i_data))
         # if not in stall condition, update the temporary register
         with m.If(self.p.o_ready): # not stalled
-            m.d.sync += self.update_buffer()
+            m.d.sync += eq(r_data, result) # update buffer
 
         #with m.If(self.p.i_rst): # reset
         #    m.d.sync += self.n.o_valid.eq(0)
@@ -235,12 +239,12 @@ class BufferedPipeline(PipelineBase):
             with m.If(self.p.o_ready): # not stalled
                 # nothing in buffer: send (processed) input direct to output
                 m.d.sync += [self.n.o_valid.eq(self.p.i_valid),
-                             self.update_output(),
+                             eq(self.n.o_data, result), # update output
                             ]
             with m.Else(): # p.o_ready is false, and something is in buffer.
                 # Flush the [already processed] buffer to the output port.
                 m.d.sync += [self.n.o_valid.eq(1),
-                             self.flush_buffer(),
+                             eq(self.n.o_data, r_data), # flush buffer
                              # clear stall condition, declare register empty.
                              self.p.o_ready.eq(1),
                             ]
@@ -251,7 +255,7 @@ class BufferedPipeline(PipelineBase):
             m.d.sync += [self.n.o_valid.eq(self.p.i_valid),
                          self.p.o_ready.eq(1), # Keep the buffer empty
                          # set the output data (from comb result)
-                         self.update_output(),
+                         eq(self.n.o_data, result),
                         ]
         # (n.i_ready) false and (n.o_valid) true:
         with m.Elif(i_p_valid_o_p_ready):
@@ -347,23 +351,24 @@ class CombPipe(PipelineBase):
 
         # set up the input and output data
         self.p.i_data = stage.ispec() # input type
-        self.r_data = stage.ispec() # input type
-        self.result = stage.ospec() # output data
         self.n.o_data = stage.ospec() # output type
-        self.n.o_data.name = "outdata"
 
     def elaborate(self, platform):
         m = Module()
+
+        r_data = self.stage.ispec() # input type
+        result = self.stage.ospec() # output data
         if hasattr(self.stage, "setup"):
-            self.stage.setup(m, self.r_data)
-        m.d.comb += eq(self.result, self.stage.process(self.r_data))
+            self.stage.setup(m, r_data)
+
+        m.d.comb += eq(result, self.stage.process(r_data))
         m.d.comb += self.n.o_valid.eq(self._data_valid)
         m.d.comb += self.p.o_ready.eq(~self._data_valid | self.n.i_ready)
         m.d.sync += self._data_valid.eq(self.p.i_valid | \
                                         (~self.n.i_ready & self._data_valid))
         with m.If(self.p.i_valid & self.p.o_ready):
-            m.d.sync += eq(self.r_data, self.p.i_data)
-        m.d.comb += eq(self.n.o_data, self.result)
+            m.d.sync += eq(r_data, self.p.i_data)
+        m.d.comb += eq(self.n.o_data, result)
         return m