X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Fexample_buf_pipe.py;h=a1f5d04f565c1ec3cd1d2f813ca3fd9436fa6216;hb=749ea1efc895d5259e49062bd9025dd6b1051636;hp=52568b5a0621ea1e440289697a8a38ae5be2380b;hpb=a1e782fa24191490825b0a43509cbb264b5cadd9;p=ieee754fpu.git

diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py
index 52568b5a..a1f5d04f 100644
--- a/src/add/example_buf_pipe.py
+++ b/src/add/example_buf_pipe.py
@@ -45,6 +45,8 @@
 
 from nmigen import Signal, Cat, Const, Mux, Module
 from nmigen.cli import verilog, rtlil
+from nmigen.hdl.rec import Record, Layout
+
 from collections.abc import Sequence
 
 
@@ -56,8 +58,8 @@ class PrevControl:
     """
 
     def __init__(self):
-        self.i_valid = Signal(name="p_i_valid") # >>in
-        self.o_ready = Signal(name="p_o_ready") # <<out
+        self.i_valid = Signal(name="p_i_valid") # prev   >>in  self
+        self.o_ready = Signal(name="p_o_ready") # prev   <<out self
 
     def connect_in(self, prev):
         """ helper function to connect stage to an input source.  do not
@@ -76,8 +78,8 @@ class NextControl:
         * o_data : an output - added by the user of this class
     """
     def __init__(self):
-        self.o_valid = Signal(name="n_o_valid") # out>>
-        self.i_ready = Signal(name="n_i_ready") # <<in
+        self.o_valid = Signal(name="n_o_valid") # self out>>  next
+        self.i_ready = Signal(name="n_i_ready") # self <<in   next
 
     def connect_to_next(self, nxt):
         """ helper function to connect to the next stage data/valid/ready.
@@ -102,12 +104,26 @@ def eq(o, i):
     """ makes signals equal: a helper routine which identifies if it is being
         passsed a list (or tuple) of objects, and calls the objects' eq
         function.
+
+        Record is a special (unusual, recursive) case, where the input
+        is specified as a dictionary (which may contain further dictionaries,
+        recursively), where the field names of the dictionary must match
+        the Record's field spec.
     """
     if not isinstance(o, Sequence):
         o, i = [o], [i]
     res = []
     for (ao, ai) in zip(o, i):
-        res.append(ao.eq(ai))
+        #print ("eq", ao, ai)
+        if isinstance(ao, Record):
+            for idx, (field_name, field_shape, _) in enumerate(ao.layout):
+                if isinstance(field_shape, Layout):
+                    rres = eq(ao.fields[field_name], ai.fields[field_name])
+                else:
+                    rres = eq(ao.fields[field_name], ai[field_name])
+                res += rres
+        else:
+            res.append(ao.eq(ai))
     return res
 
 
@@ -156,7 +172,7 @@ class PipelineBase:
     def ports(self):
         return [self.p.i_valid, self.n.i_ready,
                 self.n.o_valid, self.p.o_ready,
-                self.p.i_data, self.n.o_data
+                self.p.i_data, self.n.o_data   # XXX need flattening!
                ]