X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Fexample_buf_pipe.py;h=b83d5035cc01c7ec338c1589359323b213e3099f;hb=f3945d1317aa236b752c1e286801caa2c3a07703;hp=6d13099b93dc549b03598a43cb13cbc876681715;hpb=5aa2f167e98633cc1cf2e896d717a132e8d1721b;p=ieee754fpu.git

diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py
index 6d13099b..b83d5035 100644
--- a/src/add/example_buf_pipe.py
+++ b/src/add/example_buf_pipe.py
@@ -72,6 +72,14 @@ class PrevControl:
                 eq(self.i_data, prev.i_data),
                ]
 
+    def i_valid_logic(self):
+        vlen = len(self.i_valid)
+        if vlen > 1: # multi-bit case: valid only when i_valid is all 1s
+            all1s = Const(-1, (len(self.i_valid), False))
+            return self.i_valid == all1s
+        # single-bit i_valid case
+        return self.i_valid
+
 
 class NextControl:
     """ contains the signals that go *to* the next stage (both in and out)
@@ -104,8 +112,8 @@ class NextControl:
 
 def eq(o, i):
     """ makes signals equal: a helper routine which identifies if it is being
-        passsed a list (or tuple) of objects, and calls the objects' eq
-        function.
+        passed a list (or tuple) of objects, or signals, or Records, and calls
+        the objects' eq function.
 
         complex objects (classes) can be used: they must follow the
         convention of having an eq member function, which takes the
@@ -130,10 +138,48 @@ def eq(o, i):
                     rres = eq(ao.fields[field_name], ai[field_name])
                 res += rres
         else:
-            res.append(ao.eq(ai))
+            rres = ao.eq(ai)
+            if not isinstance(rres, Sequence):
+                rres = [rres]
+            res += rres
     return res
 
 
+class StageChain:
+    """ pass in a list of stages, and they will automatically be
+        chained together via their input and output specs into a
+        combinatorial chain.
+
+        * input to this class will be the input of the first stage
+        * output of first stage goes into input of second
+        * output of second goes into input into third (etc. etc.)
+        * the output of this class will be the output of the last stage
+    """
+    def __init__(self, chain):
+        self.chain = chain
+
+    def ispec(self):
+        return self.chain[0].ispec()
+
+    def ospec(self):
+        return self.chain[-1].ospec()
+
+    def setup(self, m, i):
+        for (idx, c) in enumerate(self.chain):
+            if hasattr(c, "setup"):
+                c.setup(m, i)               # stage may have some module stuff
+            o = self.chain[idx].ospec()     # only the last assignment survives
+            m.d.comb += eq(o, c.process(i)) # process input into "o"
+            if idx != len(self.chain)-1:
+                ni = self.chain[idx+1].ispec() # becomes new input on next loop
+                m.d.comb += eq(ni, o)          # assign output to next input
+                i = ni
+        self.o = o                             # last loop is the output
+
+    def process(self, i):
+        return self.o
+
+
 class PipelineBase:
     """ Common functions for Pipeline API
     """
@@ -227,16 +273,11 @@ class BufferedPipeline(PipelineBase):
             self.stage.setup(m, self.p.i_data)
 
         # establish some combinatorial temporaries
-        p_i_valid = Signal(reset_less=True)
         o_n_validn = Signal(reset_less=True)
         i_p_valid_o_p_ready = Signal(reset_less=True)
-        vlen = len(self.p.i_valid)
-        if vlen > 1: # multi-bit case: valid only when i_valid is all 1s
-            all1s = Const(-1, (len(self.p.i_valid), False))
-            m.d.comb += p_i_valid.eq(self.p.i_valid == all1s)
-        else: # single-bit i_valid case
-            m.d.comb += p_i_valid.eq(self.p.i_valid)
-        m.d.comb += [ o_n_validn.eq(~self.n.o_valid),
+        p_i_valid = Signal(reset_less=True)
+        m.d.comb += [p_i_valid.eq(self.p.i_valid_logic()),
+                     o_n_validn.eq(~self.n.o_valid),
                      i_p_valid_o_p_ready.eq(p_i_valid & self.p.o_ready),
         ]
 
@@ -316,10 +357,10 @@ class ExampleStage:
     """
 
     def ispec():
-        return Signal(16)
+        return Signal(16, name="example_input_signal")
 
     def ospec():
-        return Signal(16)
+        return Signal(16, name="example_output_signal")
 
     def process(i):
         """ process the input data and returns it (adds 1)
@@ -327,6 +368,23 @@ class ExampleStage:
         return i + 1
 
 
+class ExampleStageCls:
+    """ an example of how to use the buffered pipeline, in a static class
+        fashion
+    """
+
+    def ispec(self):
+        return Signal(16, name="example_input_signal")
+
+    def ospec(self):
+        return Signal(16, name="example_output_signal")
+
+    def process(self, i):
+        """ process the input data and returns it (adds 1)
+        """
+        return i + 1
+
+
 class ExampleBufPipe(BufferedPipeline):
     """ an example of how to use the buffered pipeline.
     """
@@ -367,10 +425,12 @@ class CombPipe(PipelineBase):
         if hasattr(self.stage, "setup"):
             self.stage.setup(m, r_data)
 
+        p_i_valid = Signal(reset_less=True)
+        m.d.comb += p_i_valid.eq(self.p.i_valid_logic())
         m.d.comb += eq(result, self.stage.process(r_data))
         m.d.comb += self.n.o_valid.eq(self._data_valid)
         m.d.comb += self.p.o_ready.eq(~self._data_valid | self.n.i_ready)
-        m.d.sync += self._data_valid.eq(self.p.i_valid | \
+        m.d.sync += self._data_valid.eq(p_i_valid | \
                                         (~self.n.i_ready & self._data_valid))
         with m.If(self.p.i_valid & self.p.o_ready):
             m.d.sync += eq(r_data, self.p.i_data)