X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Ffmul.py;h=0629ffb5f539defa9c665b0d2a0023e05238abd0;hb=95cd53141ace92120fccb83a96af96323dea9c0d;hp=d29d5404b552cdd6955c9bdfdf2ba25f95523fa1;hpb=d6e5544bcacbaca4934a63706892c042c01c3db7;p=ieee754fpu.git

diff --git a/src/add/fmul.py b/src/add/fmul.py
index d29d5404..0629ffb5 100644
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -1,8 +1,25 @@
-from nmigen import Module, Signal
+from nmigen import Module, Signal, Cat, Mux, Array, Const
 from nmigen.cli import main, verilog
 
 from fpbase import FPNum, FPOp, Overflow, FPBase
 
+class FPState(FPBase):
+    def __init__(self, state_from):
+        self.state_from = state_from
+
+    def set_inputs(self, inputs):
+        self.inputs = inputs
+        for k,v in inputs.items():
+            setattr(self, k, v)
+
+    def set_outputs(self, outputs):
+        self.outputs = outputs
+        for k,v in outputs.items():
+            setattr(self, k, v)
+
+'''
+
+# OLD DESIGN #
 
 class FPMUL(FPBase):
 
@@ -152,3 +169,5 @@ class FPMUL(FPBase):
 if __name__ == "__main__":
     alu = FPMUL(width=32)
     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
+    
+'''