X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Ffmul.py;h=130d49e814d05028f5248206c4e87611e304a35b;hb=286fdefc4bbe8c7b4bb34ae33b513e8bb81b3d7e;hp=8ddd45eb8bda5eb5a18dd14feeb56fab6124f876;hpb=43c53078d577aa33d28ba0eb2af782b7d348a517;p=ieee754fpu.git

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 8ddd45eb..130d49e8 100644
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -28,6 +28,10 @@ class FPMUL(FPBase):
         product = Signal(mw)
 
         of = Overflow()
+        m.submodules.of = of
+        m.submodules.a = a
+        m.submodules.b = b
+        m.submodules.z = z
 
         with m.FSM() as fsm:
 
@@ -127,7 +131,7 @@ class FPMUL(FPBase):
             # rounding stage
 
             with m.State("round"):
-                self.roundz(m, z, of)
+                self.roundz(m, z, of.roundz)
                 m.next = "corrections"
 
             # ******