X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Ffmul.py;h=46ad8099874b28899484477e321a9b3171c56db1;hb=5ca9e3ee685a261fbff9998ab37940aa3255b9fa;hp=0629ffb5f539defa9c665b0d2a0023e05238abd0;hpb=95cd53141ace92120fccb83a96af96323dea9c0d;p=ieee754fpu.git

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 0629ffb5..46ad8099 100644
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -2,24 +2,7 @@ from nmigen import Module, Signal, Cat, Mux, Array, Const
 from nmigen.cli import main, verilog
 
 from fpbase import FPNum, FPOp, Overflow, FPBase
-
-class FPState(FPBase):
-    def __init__(self, state_from):
-        self.state_from = state_from
-
-    def set_inputs(self, inputs):
-        self.inputs = inputs
-        for k,v in inputs.items():
-            setattr(self, k, v)
-
-    def set_outputs(self, outputs):
-        self.outputs = outputs
-        for k,v in outputs.items():
-            setattr(self, k, v)
-
-'''
-
-# OLD DESIGN #
+from nmigen_add_experiment import FPState
 
 class FPMUL(FPBase):
 
@@ -169,5 +152,3 @@ class FPMUL(FPBase):
 if __name__ == "__main__":
     alu = FPMUL(width=32)
     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
-    
-'''