X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Ffmul.py;h=9ed2bf39b9bb67392c602b91484e8b8fdf47ce17;hb=892d640f8224e6a52907c6899ab6ab671f5f53af;hp=d29d5404b552cdd6955c9bdfdf2ba25f95523fa1;hpb=d6e5544bcacbaca4934a63706892c042c01c3db7;p=ieee754fpu.git

diff --git a/src/add/fmul.py b/src/add/fmul.py
index d29d5404..9ed2bf39 100644
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -1,8 +1,8 @@
-from nmigen import Module, Signal
+from nmigen import Module, Signal, Cat, Mux, Array, Const
 from nmigen.cli import main, verilog
 
-from fpbase import FPNum, FPOp, Overflow, FPBase
-
+from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
+from nmigen_add_experiment import FPState
 
 class FPMUL(FPBase):
 
@@ -20,9 +20,9 @@ class FPMUL(FPBase):
         m = Module()
 
         # Latches
-        a = FPNum(self.width, False)
-        b = FPNum(self.width, False)
-        z = FPNum(self.width, False)
+        a = FPNumIn(None, self.width, False)
+        b = FPNumIn(None, self.width, False)
+        z = FPNumOut(self.width, False)
 
         mw = (z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
         product = Signal(mw)
@@ -48,30 +48,30 @@ class FPMUL(FPBase):
 
             with m.State("special_cases"):
                 #if a or b is NaN return NaN
-                with m.If(a.is_nan() | b.is_nan()):
+                with m.If(a.is_nan | b.is_nan):
                     m.next = "put_z"
                     m.d.sync += z.nan(1)
                 #if a is inf return inf
-                with m.Elif(a.is_inf()):
+                with m.Elif(a.is_inf):
                     m.next = "put_z"
                     m.d.sync += z.inf(a.s ^ b.s)
                     #if b is zero return NaN
-                    with m.If(b.is_zero()):
+                    with m.If(b.is_zero):
                         m.d.sync += z.nan(1)
                 #if b is inf return inf
-                with m.Elif(b.is_inf()):
+                with m.Elif(b.is_inf):
                     m.next = "put_z"
                     m.d.sync += z.inf(a.s ^ b.s)
                     #if a is zero return NaN
-                    with m.If(a.is_zero()):
+                    with m.If(a.is_zero):
                         m.next = "put_z"
                         m.d.sync += z.nan(1)
                 #if a is zero return zero
-                with m.Elif(a.is_zero()):
+                with m.Elif(a.is_zero):
                     m.next = "put_z"
                     m.d.sync += z.zero(a.s ^ b.s)
                 #if b is zero return zero
-                with m.Elif(b.is_zero()):
+                with m.Elif(b.is_zero):
                     m.next = "put_z"
                     m.d.sync += z.zero(a.s ^ b.s)
                 # Denormalised Number checks
@@ -127,7 +127,8 @@ class FPMUL(FPBase):
             # rounding stage
 
             with m.State("round"):
-                self.roundz(m, z, of, "corrections")
+                #self.roundz(m, z, of.roundz)
+                m.next = "corrections"
 
             # ******
             # correction stage