X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Ffmul.py;h=a2ba41e75eb9bbf081d20158865171c21911940d;hb=6bff1a997f3846872cf489c24b5c01426c4dc97c;hp=0629ffb5f539defa9c665b0d2a0023e05238abd0;hpb=95cd53141ace92120fccb83a96af96323dea9c0d;p=ieee754fpu.git

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 0629ffb5..a2ba41e7 100644
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -1,25 +1,10 @@
 from nmigen import Module, Signal, Cat, Mux, Array, Const
 from nmigen.cli import main, verilog
 
-from fpbase import FPNum, FPOp, Overflow, FPBase
+from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPState
+from fpcommon.getop import FPGetOp
+from singlepipe import eq
 
-class FPState(FPBase):
-    def __init__(self, state_from):
-        self.state_from = state_from
-
-    def set_inputs(self, inputs):
-        self.inputs = inputs
-        for k,v in inputs.items():
-            setattr(self, k, v)
-
-    def set_outputs(self, outputs):
-        self.outputs = outputs
-        for k,v in outputs.items():
-            setattr(self, k, v)
-
-'''
-
-# OLD DESIGN #
 
 class FPMUL(FPBase):
 
@@ -31,20 +16,33 @@ class FPMUL(FPBase):
         self.in_b  = FPOp(width)
         self.out_z = FPOp(width)
 
-    def get_fragment(self, platform=None):
+        self.states = []
+
+    def add_state(self, state):
+        self.states.append(state)
+        return state
+
+    def elaborate(self, platform=None):
         """ creates the HDL code-fragment for FPMUL
         """
         m = Module()
 
         # Latches
-        a = FPNum(self.width, False)
-        b = FPNum(self.width, False)
-        z = FPNum(self.width, False)
+        a = FPNumIn(None, self.width, False)
+        b = FPNumIn(None, self.width, False)
+        z = FPNumOut(self.width, False)
 
         mw = (z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
         product = Signal(mw)
 
         of = Overflow()
+        m.submodules.of = of
+        m.submodules.a = a
+        m.submodules.b = b
+        m.submodules.z = z
+
+        m.d.comb += a.v.eq(self.in_a.v)
+        m.d.comb += b.v.eq(self.in_b.v)
 
         with m.FSM() as fsm:
 
@@ -52,43 +50,45 @@ class FPMUL(FPBase):
             # gets operand a
 
             with m.State("get_a"):
-                self.get_op(m, self.in_a, a, "get_b")
+                res = self.get_op(m, self.in_a, a, "get_b")
+                m.d.sync += eq([a, self.in_a.ack], res)
 
             # ******
             # gets operand b
 
             with m.State("get_b"):
-                self.get_op(m, self.in_b, b, "special_cases")
+                res = self.get_op(m, self.in_b, b, "special_cases")
+                m.d.sync += eq([b, self.in_b.ack], res)
 
             # ******
             # special cases
 
             with m.State("special_cases"):
                 #if a or b is NaN return NaN
-                with m.If(a.is_nan() | b.is_nan()):
+                with m.If(a.is_nan | b.is_nan):
                     m.next = "put_z"
                     m.d.sync += z.nan(1)
                 #if a is inf return inf
-                with m.Elif(a.is_inf()):
+                with m.Elif(a.is_inf):
                     m.next = "put_z"
                     m.d.sync += z.inf(a.s ^ b.s)
                     #if b is zero return NaN
-                    with m.If(b.is_zero()):
+                    with m.If(b.is_zero):
                         m.d.sync += z.nan(1)
                 #if b is inf return inf
-                with m.Elif(b.is_inf()):
+                with m.Elif(b.is_inf):
                     m.next = "put_z"
                     m.d.sync += z.inf(a.s ^ b.s)
                     #if a is zero return NaN
-                    with m.If(a.is_zero()):
+                    with m.If(a.is_zero):
                         m.next = "put_z"
                         m.d.sync += z.nan(1)
                 #if a is zero return zero
-                with m.Elif(a.is_zero()):
+                with m.Elif(a.is_zero):
                     m.next = "put_z"
                     m.d.sync += z.zero(a.s ^ b.s)
                 #if b is zero return zero
-                with m.Elif(b.is_zero()):
+                with m.Elif(b.is_zero):
                     m.next = "put_z"
                     m.d.sync += z.zero(a.s ^ b.s)
                 # Denormalised Number checks
@@ -144,7 +144,8 @@ class FPMUL(FPBase):
             # rounding stage
 
             with m.State("round"):
-                self.roundz(m, z, of, "corrections")
+                self.roundz(m, z, of.roundz)
+                m.next = "corrections"
 
             # ******
             # correction stage
@@ -169,5 +170,3 @@ class FPMUL(FPBase):
 if __name__ == "__main__":
     alu = FPMUL(width=32)
     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
-    
-'''