X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Ffmul.py;h=a2ba41e75eb9bbf081d20158865171c21911940d;hb=6bff1a997f3846872cf489c24b5c01426c4dc97c;hp=130d49e814d05028f5248206c4e87611e304a35b;hpb=286fdefc4bbe8c7b4bb34ae33b513e8bb81b3d7e;p=ieee754fpu.git

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 130d49e8..a2ba41e7 100644
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -1,8 +1,10 @@
 from nmigen import Module, Signal, Cat, Mux, Array, Const
 from nmigen.cli import main, verilog
 
-from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
-from nmigen_add_experiment import FPState
+from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPState
+from fpcommon.getop import FPGetOp
+from singlepipe import eq
+
 
 class FPMUL(FPBase):
 
@@ -14,7 +16,13 @@ class FPMUL(FPBase):
         self.in_b  = FPOp(width)
         self.out_z = FPOp(width)
 
-    def get_fragment(self, platform=None):
+        self.states = []
+
+    def add_state(self, state):
+        self.states.append(state)
+        return state
+
+    def elaborate(self, platform=None):
         """ creates the HDL code-fragment for FPMUL
         """
         m = Module()
@@ -33,19 +41,24 @@ class FPMUL(FPBase):
         m.submodules.b = b
         m.submodules.z = z
 
+        m.d.comb += a.v.eq(self.in_a.v)
+        m.d.comb += b.v.eq(self.in_b.v)
+
         with m.FSM() as fsm:
 
             # ******
             # gets operand a
 
             with m.State("get_a"):
-                self.get_op(m, self.in_a, a, "get_b")
+                res = self.get_op(m, self.in_a, a, "get_b")
+                m.d.sync += eq([a, self.in_a.ack], res)
 
             # ******
             # gets operand b
 
             with m.State("get_b"):
-                self.get_op(m, self.in_b, b, "special_cases")
+                res = self.get_op(m, self.in_b, b, "special_cases")
+                m.d.sync += eq([b, self.in_b.ack], res)
 
             # ******
             # special cases