X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Ffpadd%2Fadd1.py;h=679f5176d2d9227c41637d9fb9db2d6c08c6845d;hb=6bff1a997f3846872cf489c24b5c01426c4dc97c;hp=76fd968a5578761af35266868506cdf6cf810668;hpb=ddadc015b62086dbefe3276c722b21b2b628adfd;p=ieee754fpu.git

diff --git a/src/add/fpadd/add1.py b/src/add/fpadd/add1.py
index 76fd968a..679f5176 100644
--- a/src/add/fpadd/add1.py
+++ b/src/add/fpadd/add1.py
@@ -2,37 +2,16 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Cat, Mux, Array, Const
-from nmigen.lib.coding import PriorityEncoder
+from nmigen import Module, Signal, Elaboratable
 from nmigen.cli import main, verilog
 from math import log
 
-from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
-from fpbase import MultiShiftRMerge, Trigger
-from singlepipe import (ControlBase, StageChain, UnbufferedPipeline,
-                        PassThroughStage)
-from multipipe import CombMuxOutPipe
-from multipipe import PriorityCombMuxInPipe
-
-from fpbase import FPState, FPID
-from fpcommon.denorm import (FPSCData, FPAddDeNormMod, FPAddDeNorm)
+from fpbase import FPState
 from fpcommon.postcalc import FPAddStage1Data
-from fpcommon.postnormalise import (FPNorm1Data, FPNorm1ModSingle,
-                            FPNorm1ModMulti, FPNorm1Single, FPNorm1Multi)
-from fpcommon.roundz import (FPRoundData, FPRoundMod, FPRound)
-from fpcommon.corrections import (FPCorrectionsMod, FPCorrections)
-from fpcommon.pack import (FPPackData, FPPackMod, FPPack)
-from fpcommon.normtopack import FPNormToPack
-from fpcommon.putz import (FPPutZ, FPPutZIdx)
-
-from fpadd.specialcases import (FPAddSpecialCasesMod, FPAddSpecialCases,
-                                FPAddSpecialCasesDeNorm)
-from fpadd.align import (FPAddAlignMulti, FPAddAlignMultiMod, FPNumIn2Ops,
-                         FPAddAlignSingleMod, FPAddAlignSingle)
-from fpadd.add0 import (FPAddStage0Data, FPAddStage0Mod, FPAddStage0)
-
-
-class FPAddStage1Mod(FPState):
+from fpadd.add0 import FPAddStage0Data
+
+
+class FPAddStage1Mod(FPState, Elaboratable):
     """ Second stage of add: preparation for normalisation.
         detects when tot sum is too big (tot[27] is kinda a carry bit)
     """