X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Ffpadd%2Fpipeline.py;h=e244ee60e2f373d917de6eaeaca4a6e7f74d9f32;hb=6bff1a997f3846872cf489c24b5c01426c4dc97c;hp=22eed7e0dfd9b3ec27f21152bac67e01f4b8c66d;hpb=770e827b0a3473d4ba6947161790f04bfec252e5;p=ieee754fpu.git

diff --git a/src/add/fpadd/pipeline.py b/src/add/fpadd/pipeline.py
index 22eed7e0..e244ee60 100644
--- a/src/add/fpadd/pipeline.py
+++ b/src/add/fpadd/pipeline.py
@@ -5,7 +5,7 @@
 from nmigen import Module
 from nmigen.cli import main, verilog
 
-from singlepipe import (ControlBase, UnbufferedPipeline, PassThroughStage)
+from singlepipe import (ControlBase, SimpleHandshake, PassThroughStage)
 from multipipe import CombMuxOutPipe
 from multipipe import PriorityCombMuxInPipe
 
@@ -16,6 +16,8 @@ from fpcommon.normtopack import FPNormToPack
 from fpadd.specialcases import FPAddSpecialCasesDeNorm
 from fpadd.addstages import FPAddAlignSingleAdd
 
+from concurrentunit import ReservationStations, num_bits
+
 
 class FPADDBasePipe(ControlBase):
     def __init__(self, width, id_wid):
@@ -27,7 +29,7 @@ class FPADDBasePipe(ControlBase):
         self._eqs = self.connect([self.pipe1, self.pipe2, self.pipe3])
 
     def elaborate(self, platform):
-        m = Module()
+        m = ControlBase.elaborate(self, platform)
         m.submodules.scnorm = self.pipe1
         m.submodules.addalign = self.pipe2
         m.submodules.normpack = self.pipe3
@@ -35,23 +37,7 @@ class FPADDBasePipe(ControlBase):
         return m
 
 
-class FPADDInMuxPipe(PriorityCombMuxInPipe):
-    def __init__(self, width, id_wid, num_rows):
-        self.num_rows = num_rows
-        def iospec(): return FPADDBaseData(width, id_wid)
-        stage = PassThroughStage(iospec)
-        PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows)
-
-
-class FPADDMuxOutPipe(CombMuxOutPipe):
-    def __init__(self, width, id_wid, num_rows):
-        self.num_rows = num_rows
-        def iospec(): return FPPackData(width, id_wid)
-        stage = PassThroughStage(iospec)
-        CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
-
-
-class FPADDMuxInOut:
+class FPADDMuxInOut(ReservationStations):
     """ Reservation-Station version of FPADD pipeline.
 
         * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
@@ -60,28 +46,14 @@ class FPADDMuxInOut:
 
         Fan-in and Fan-out are combinatorial.
     """
-    def __init__(self, width, id_wid, num_rows):
-        self.num_rows = num_rows
-        self.inpipe = FPADDInMuxPipe(width, id_wid, num_rows)   # fan-in
-        self.fpadd = FPADDBasePipe(width, id_wid)               # add stage
-        self.outpipe = FPADDMuxOutPipe(width, id_wid, num_rows) # fan-out
-
-        self.p = self.inpipe.p  # kinda annoying,
-        self.n = self.outpipe.n # use pipe in/out as this class in/out
-        self._ports = self.inpipe.ports() + self.outpipe.ports()
-
-    def elaborate(self, platform):
-        m = Module()
-        m.submodules.inpipe = self.inpipe
-        m.submodules.fpadd = self.fpadd
-        m.submodules.outpipe = self.outpipe
-
-        m.d.comb += self.inpipe.n.connect_to_next(self.fpadd.p)
-        m.d.comb += self.fpadd.connect_to_next(self.outpipe)
-
-        return m
-
-    def ports(self):
-        return self._ports
+    def __init__(self, width, num_rows):
+        self.width = width
+        self.id_wid = num_bits(width)
+        self.alu = FPADDBasePipe(width, self.id_wid)
+        ReservationStations.__init__(self, num_rows)
 
+    def i_specfn(self):
+        return FPADDBaseData(self.width, self.id_wid)
 
+    def o_specfn(self):
+        return FPPackData(self.width, self.id_wid)