X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Fnmigen_add_experiment.py;h=71db07a44a3dccf722c2535992555963ca156f28;hb=19b4593a2fdd2b74c0d68828ca3666469518b9b0;hp=02d60c1bab3afb0f2dbc0493048334af1945498e;hpb=8fdf4e8fc4f0ffe3c04cf028bd615008eed8f530;p=ieee754fpu.git

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 02d60c1b..71db07a4 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -937,7 +937,7 @@ class FPNormaliseModSingle:
     def ospec(self):
         return FPNumBase(self.width, False)
 
-    def setup(self, m, in_z, out_z, modname):
+    def setup(self, m, in_z, out_z):
         """ links module to inputs and outputs
         """
         m.submodules.normalise = self
@@ -992,6 +992,16 @@ class FPNormaliseModSingle:
 
         return m
 
+class FPNorm1Data:
+
+    def __init__(self, width):
+
+        self.roundz = Signal(reset_less=True)
+        self.z = FPNumBase(width, False)
+
+    def eq(self, i):
+        return [self.z.eq(i.z), self.roundz.eq(i.roundz)]
+
 
 class FPNorm1ModSingle:
 
@@ -1004,7 +1014,7 @@ class FPNorm1ModSingle:
         return FPAddStage1Data(self.width)
 
     def ospec(self):
-        return FPAddStage1Data(self.width)
+        return FPAddStage1Data(self.width) # XXX TODO: FPNorm1Data
 
     def setup(self, m, in_z, in_of, out_z):
         """ links module to inputs and outputs
@@ -1165,8 +1175,7 @@ class FPNorm1Single(FPState, FPID):
         FPID.__init__(self, id_wid)
         FPState.__init__(self, "normalise_1")
         self.mod = FPNorm1ModSingle(width)
-        self.out_norm = Signal(reset_less=True)
-        self.out_z = FPNumBase(width)
+        self.out_z = FPNumBase(width, False)
         self.out_roundz = Signal(reset_less=True)
 
     def setup(self, m, in_z, in_of, in_mid):
@@ -1249,20 +1258,20 @@ class FPNormToPack(FPState, FPID):
 
         # Rounding (chained to normalisation)
         rmod = FPRoundMod(self.width)
-        r_out_z = FPNumBase(self.width)
+        r_out_z = rmod.ospec()
         rmod.setup(m, n_out_z, n_out_roundz)
         m.d.comb += n_out_roundz.eq(nmod.o.of.roundz)
         m.d.comb += r_out_z.eq(rmod.out_z)
 
         # Corrections (chained to rounding)
         cmod = FPCorrectionsMod(self.width)
-        c_out_z = FPNumBase(self.width)
+        c_out_z = cmod.ospec()
         cmod.setup(m, r_out_z)
         m.d.comb += c_out_z.eq(cmod.out_z)
 
         # Pack (chained to corrections)
         self.pmod = FPPackMod(self.width)
-        self.out_z = FPNumBase(self.width)
+        self.out_z = self.pmod.ospec()
         self.pmod.setup(m, c_out_z)
 
         # Multiplex ID
@@ -1278,23 +1287,29 @@ class FPNormToPack(FPState, FPID):
 class FPRoundMod:
 
     def __init__(self, width):
-        self.in_roundz = Signal(reset_less=True)
-        self.in_z = FPNumBase(width, False)
-        self.out_z = FPNumBase(width, False)
+        self.width = width
+        self.i = self.ispec()
+        self.out_z = self.ospec()
+
+    def ispec(self):
+        return FPNorm1Data(self.width)
+
+    def ospec(self):
+        return FPNumBase(self.width, False)
 
     def setup(self, m, in_z, roundz):
         m.submodules.roundz = self
 
-        m.d.comb += self.in_z.eq(in_z)
-        m.d.comb += self.in_roundz.eq(roundz)
+        m.d.comb += self.i.z.eq(in_z)
+        m.d.comb += self.i.roundz.eq(roundz)
 
     def elaborate(self, platform):
         m = Module()
-        m.d.comb += self.out_z.eq(self.in_z)
-        with m.If(self.in_roundz):
-            m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
-            with m.If(self.in_z.m == self.in_z.m1s): # all 1s
-                m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
+        m.d.comb += self.out_z.eq(self.i.z)
+        with m.If(self.i.roundz):
+            m.d.comb += self.out_z.m.eq(self.i.z.m + 1) # mantissa rounds up
+            with m.If(self.i.z.m == self.i.z.m1s): # all 1s
+                m.d.comb += self.out_z.e.eq(self.i.z.e + 1) # exponent up
         return m
 
 
@@ -1304,7 +1319,7 @@ class FPRound(FPState, FPID):
         FPState.__init__(self, "round")
         FPID.__init__(self, id_wid)
         self.mod = FPRoundMod(width)
-        self.out_z = FPNumBase(width)
+        self.out_z = self.mod.ospec()
 
     def setup(self, m, in_z, roundz, in_mid):
         """ links module to inputs and outputs
@@ -1323,8 +1338,15 @@ class FPRound(FPState, FPID):
 class FPCorrectionsMod:
 
     def __init__(self, width):
-        self.in_z = FPNumOut(width, False)
-        self.out_z = FPNumOut(width, False)
+        self.width = width
+        self.in_z = self.ispec()
+        self.out_z = self.ospec()
+
+    def ispec(self):
+        return FPNumOut(self.width, False)
+
+    def ospec(self):
+        return FPNumOut(self.width, False)
 
     def setup(self, m, in_z):
         """ links module to inputs and outputs
@@ -1348,7 +1370,7 @@ class FPCorrections(FPState, FPID):
         FPState.__init__(self, "corrections")
         FPID.__init__(self, id_wid)
         self.mod = FPCorrectionsMod(width)
-        self.out_z = FPNumBase(width)
+        self.out_z = self.mod.ospec()
 
     def setup(self, m, in_z, in_mid):
         """ links module to inputs and outputs
@@ -1366,8 +1388,15 @@ class FPCorrections(FPState, FPID):
 class FPPackMod:
 
     def __init__(self, width):
-        self.in_z = FPNumOut(width, False)
-        self.out_z = FPNumOut(width, False)
+        self.width = width
+        self.in_z = self.ispec()
+        self.out_z = self.ospec()
+
+    def ispec(self):
+        return FPNumOut(self.width, False)
+
+    def ospec(self):
+        return FPNumOut(self.width, False)
 
     def setup(self, m, in_z):
         """ links module to inputs and outputs
@@ -1391,7 +1420,7 @@ class FPPack(FPState, FPID):
         FPState.__init__(self, "pack")
         FPID.__init__(self, id_wid)
         self.mod = FPPackMod(width)
-        self.out_z = FPNumOut(width, False)
+        self.out_z = self.mod.ospec()
 
     def setup(self, m, in_z, in_mid):
         """ links module to inputs and outputs