X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Fqueue.py;h=0038953d6ea8b3d33fd21273219f4922a725101b;hb=6bff1a997f3846872cf489c24b5c01426c4dc97c;hp=cb9e98e570e40cb70b6b2bdc0b73f1c1169ce9f3;hpb=863928452b9714bc702867003cda2a8338440dc7;p=ieee754fpu.git

diff --git a/src/add/queue.py b/src/add/queue.py
index cb9e98e5..0038953d 100644
--- a/src/add/queue.py
+++ b/src/add/queue.py
@@ -35,13 +35,16 @@ class Queue(FIFOInterface, Elaboratable):
     def __init__(self, width, depth, fwft=True, pipe=False):
         """ Queue (FIFO) with pipe mode and first-write fall-through capability
 
-            * width: width of Queue data in/out
-            * depth: queue depth.  NOTE: may be set to 0 (this is ok)
-            * fwft : first-write, fall-through mode (Chisel Queue "flow" mode)
-            * pipe : pipe mode.  NOTE: this mode can cause unanticipated
-                     problems.  when read is enabled, so is writeable.
-                     therefore if read is enabled, the data ABSOLUTELY MUST
-                     be read.
+            * :width: width of Queue data in/out
+            * :depth: queue depth.  NOTE: may be set to 0 (this is ok)
+            * :fwft : first-write, fall-through mode (Chisel Queue "flow" mode)
+            * :pipe : pipe mode.  NOTE: this mode can cause unanticipated
+                      problems.  when read is enabled, so is writeable.
+                      therefore if read is enabled, the data ABSOLUTELY MUST
+                      be read.
+
+            fwft mode = True basically means that the data may be transferred
+            combinatorially from input to output.
 
             Attributes:
             * level: available free space (number of unread entries)
@@ -67,8 +70,8 @@ class Queue(FIFOInterface, Elaboratable):
         p_valid_i = self.we
         enq_data = self.din
 
-        n_o_valid = self.readable
-        n_i_ready = self.re
+        n_valid_o = self.readable
+        n_ready_i = self.re
         deq_data = self.dout
 
         # intermediaries
@@ -94,10 +97,10 @@ class Queue(FIFOInterface, Elaboratable):
                      empty.eq(ptr_match & ~maybe_full),
                      full.eq(ptr_match & maybe_full),
                      do_enq.eq(p_ready_o & p_valid_i), # write conditions ok
-                     do_deq.eq(n_i_ready & n_o_valid), # read conditions ok
+                     do_deq.eq(n_ready_i & n_valid_o), # read conditions ok
 
                      # set readable and writable (NOTE: see pipe mode below)
-                     n_o_valid.eq(~empty), # cannot read if empty!
+                     n_valid_o.eq(~empty), # cannot read if empty!
                      p_ready_o.eq(~full),  # cannot write if full!
 
                      # set up memory and connect to input and output
@@ -128,17 +131,17 @@ class Queue(FIFOInterface, Elaboratable):
         # as Memory "write-through"... without relying on a changing API
         if self.fwft:
             with m.If(p_valid_i):
-                m.d.comb += n_o_valid.eq(1)
+                m.d.comb += n_valid_o.eq(1)
             with m.If(empty):
                 m.d.comb += deq_data.eq(enq_data)
                 m.d.comb += do_deq.eq(0)
-                with m.If(n_i_ready):
+                with m.If(n_ready_i):
                     m.d.comb += do_enq.eq(0)
 
         # pipe mode: if next stage says it's ready (readable), we
         #            *must* declare the input ready (writeable).
         if self.pipe:
-            with m.If(n_i_ready):
+            with m.If(n_ready_i):
                 m.d.comb += p_ready_o.eq(1)
 
         # set the count (available free space), optimise on power-of-two
@@ -179,6 +182,7 @@ if __name__ == "__main__":
             m.d.comb += port.eq(signal)
             retval.append(signal)
         return retval
+
     m.submodules.reg_stage = reg_stage
     ports += queue_ports(reg_stage, "reg_stage_")
     m.submodules.break_ready_chain_stage = break_ready_chain_stage