X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Ftest_buf_pipe.py;h=37f2b31f8b0a3ce38d2067b569a28344e6ab7fd9;hb=6bff1a997f3846872cf489c24b5c01426c4dc97c;hp=441e5d9441da62a8fc9efb9d6d375318b51f5360;hpb=83144c79c0913c09ba3aa090676d80b306854c3b;p=ieee754fpu.git diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py index 441e5d94..37f2b31f 100644 --- a/src/add/test_buf_pipe.py +++ b/src/add/test_buf_pipe.py @@ -1,4 +1,20 @@ -from nmigen import Module, Signal, Mux +""" Unit tests for Buffered and Unbuffered pipelines + + contains useful worked examples of how to use the Pipeline API, + including: + + * Combinatorial Stage "Chaining" + * class-based data stages + * nmigen module-based data stages + * special nmigen module-based data stage, where the stage *is* the module + * Record-based data stages + * static-class data stages + * multi-stage pipelines (and how to connect them) + * how to *use* the pipelines (see Test5) - how to get data in and out + +""" + +from nmigen import Module, Signal, Mux, Const, Elaboratable from nmigen.hdl.rec import Record from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil @@ -6,48 +22,56 @@ from nmigen.cli import verilog, rtlil from example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd from example_buf_pipe import ExamplePipeline, UnbufferedPipeline from example_buf_pipe import ExampleStageCls -from example_buf_pipe import PrevControl, NextControl, BufferedPipeline -from example_buf_pipe import StageChain +from example_buf_pipe import PrevControl, NextControl, BufferedHandshake +from example_buf_pipe import StageChain, ControlBase, StageCls +from singlepipe import UnbufferedPipeline2 +from singlepipe import SimpleHandshake +from singlepipe import PassThroughHandshake +from singlepipe import PassThroughStage +from singlepipe import FIFOControl +from singlepipe import RecordObject + +from random import randint, seed -from random import randint +#seed(4) def check_o_n_valid(dut, val): - o_n_valid = yield dut.n[0].o_valid + o_n_valid = yield dut.n.valid_o assert o_n_valid == val def check_o_n_valid2(dut, val): - o_n_valid = yield dut.n.o_valid + o_n_valid = yield dut.n.valid_o assert o_n_valid == val -def testbench(dut): +def tbench(dut): #yield dut.i_p_rst.eq(1) - yield dut.n[0].i_ready.eq(0) - yield dut.p[0].o_ready.eq(0) + yield dut.n.ready_i.eq(0) + #yield dut.p.ready_o.eq(0) yield yield #yield dut.i_p_rst.eq(0) - yield dut.n[0].i_ready.eq(1) - yield dut.p[0].i_data.eq(5) - yield dut.p[0].i_valid.eq(1) + yield dut.n.ready_i.eq(1) + yield dut.p.data_i.eq(5) + yield dut.p.valid_i.eq(1) yield - yield dut.p[0].i_data.eq(7) + yield dut.p.data_i.eq(7) yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed yield yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt - yield dut.p[0].i_data.eq(2) + yield dut.p.data_i.eq(2) yield - yield dut.n[0].i_ready.eq(0) # begin going into "stall" (next stage says ready) - yield dut.p[0].i_data.eq(9) + yield dut.n.ready_i.eq(0) # begin going into "stall" (next stage says ready) + yield dut.p.data_i.eq(9) yield - yield dut.p[0].i_valid.eq(0) - yield dut.p[0].i_data.eq(12) + yield dut.p.valid_i.eq(0) + yield dut.p.data_i.eq(12) yield - yield dut.p[0].i_data.eq(32) - yield dut.n[0].i_ready.eq(1) + yield dut.p.data_i.eq(32) + yield dut.n.ready_i.eq(1) yield yield from check_o_n_valid(dut, 1) # buffer still needs to output yield @@ -57,34 +81,34 @@ def testbench(dut): yield -def testbench2(dut): +def tbench2(dut): #yield dut.p.i_rst.eq(1) - yield dut.n.i_ready.eq(0) - #yield dut.p.o_ready.eq(0) + yield dut.n.ready_i.eq(0) + #yield dut.p.ready_o.eq(0) yield yield #yield dut.p.i_rst.eq(0) - yield dut.n.i_ready.eq(1) - yield dut.p.i_data.eq(5) - yield dut.p.i_valid.eq(1) + yield dut.n.ready_i.eq(1) + yield dut.p.data_i.eq(5) + yield dut.p.valid_i.eq(1) yield - yield dut.p.i_data.eq(7) + yield dut.p.data_i.eq(7) yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks yield yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks - yield dut.p.i_data.eq(2) + yield dut.p.data_i.eq(2) yield yield from check_o_n_valid2(dut, 1) # ok *now* i_p_valid effect is felt - yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready) - yield dut.p.i_data.eq(9) + yield dut.n.ready_i.eq(0) # begin going into "stall" (next stage says ready) + yield dut.p.data_i.eq(9) yield - yield dut.p.i_valid.eq(0) - yield dut.p.i_data.eq(12) + yield dut.p.valid_i.eq(0) + yield dut.p.data_i.eq(12) yield - yield dut.p.i_data.eq(32) - yield dut.n.i_ready.eq(1) + yield dut.p.data_i.eq(32) + yield dut.n.ready_i.eq(1) yield yield from check_o_n_valid2(dut, 1) # buffer still needs to output yield @@ -117,16 +141,16 @@ class Test3: send = True else: send = randint(0, send_range) != 0 - o_p_ready = yield self.dut.p[0].o_ready + o_p_ready = yield self.dut.p.ready_o if not o_p_ready: yield continue if send and self.i != len(self.data): - yield self.dut.p[0].i_valid.eq(1) - yield self.dut.p[0].i_data.eq(self.data[self.i]) + yield self.dut.p.valid_i.eq(1) + yield self.dut.p.data_i.eq(self.data[self.i]) self.i += 1 else: - yield self.dut.p[0].i_valid.eq(0) + yield self.dut.p.valid_i.eq(0) yield def rcv(self): @@ -134,22 +158,22 @@ class Test3: stall_range = randint(0, 3) for j in range(randint(1,10)): stall = randint(0, stall_range) != 0 - yield self.dut.n[0].i_ready.eq(stall) + yield self.dut.n.ready_i.eq(stall) yield - o_n_valid = yield self.dut.n[0].o_valid - i_n_ready = yield self.dut.n[0].i_ready + o_n_valid = yield self.dut.n.valid_o + i_n_ready = yield self.dut.n.ready_i_test if not o_n_valid or not i_n_ready: continue - o_data = yield self.dut.n[0].o_data - self.resultfn(o_data, self.data[self.o], self.i, self.o) + data_o = yield self.dut.n.data_o + self.resultfn(data_o, self.data[self.o], self.i, self.o) self.o += 1 if self.o == len(self.data): break -def test3_resultfn(o_data, expected, i, o): - assert o_data == expected + 1, \ +def resultfn_3(data_o, expected, i, o): + assert data_o == expected + 1, \ "%d-%d data %x not match %x\n" \ - % (i, o, o_data, expected) + % (i, o, data_o, expected) def data_placeholder(): data = [] @@ -169,9 +193,10 @@ def data_dict(): class Test5: - def __init__(self, dut, resultfn, data=None): + def __init__(self, dut, resultfn, data=None, stage_ctl=False): self.dut = dut self.resultfn = resultfn + self.stage_ctl = stage_ctl if data: self.data = data else: @@ -189,49 +214,51 @@ class Test5: send = True else: send = randint(0, send_range) != 0 - o_p_ready = yield self.dut.p[0].o_ready + #send = True + o_p_ready = yield self.dut.p.ready_o if not o_p_ready: yield continue if send and self.i != len(self.data): - yield self.dut.p[0].i_valid.eq(1) + yield self.dut.p.valid_i.eq(1) for v in self.dut.set_input(self.data[self.i]): yield v self.i += 1 else: - yield self.dut.p[0].i_valid.eq(0) + yield self.dut.p.valid_i.eq(0) yield def rcv(self): while self.o != len(self.data): stall_range = randint(0, 3) for j in range(randint(1,10)): - stall = randint(0, stall_range) != 0 - yield self.dut.n[0].i_ready.eq(stall) + ready = randint(0, stall_range) != 0 + #ready = True + yield self.dut.n.ready_i.eq(ready) yield - o_n_valid = yield self.dut.n[0].o_valid - i_n_ready = yield self.dut.n[0].i_ready + o_n_valid = yield self.dut.n.valid_o + i_n_ready = yield self.dut.n.ready_i_test if not o_n_valid or not i_n_ready: continue - if isinstance(self.dut.n[0].o_data, Record): - o_data = {} - dod = self.dut.n[0].o_data + if isinstance(self.dut.n.data_o, Record): + data_o = {} + dod = self.dut.n.data_o for k, v in dod.fields.items(): - o_data[k] = yield v + data_o[k] = yield v else: - o_data = yield self.dut.n[0].o_data - self.resultfn(o_data, self.data[self.o], self.i, self.o) + data_o = yield self.dut.n.data_o + self.resultfn(data_o, self.data[self.o], self.i, self.o) self.o += 1 if self.o == len(self.data): break -def test5_resultfn(o_data, expected, i, o): +def resultfn_5(data_o, expected, i, o): res = expected[0] + expected[1] - assert o_data == res, \ + assert data_o == res, \ "%d-%d data %x not match %s\n" \ - % (i, o, o_data, repr(expected)) + % (i, o, data_o, repr(expected)) -def testbench4(dut): +def tbench4(dut): data = [] for i in range(num_tests): #data.append(randint(0, 1<<16-1)) @@ -241,72 +268,60 @@ def testbench4(dut): while True: stall = randint(0, 3) != 0 send = randint(0, 5) != 0 - yield dut.n.i_ready.eq(stall) - o_p_ready = yield dut.p.o_ready + yield dut.n.ready_i.eq(stall) + o_p_ready = yield dut.p.ready_o if o_p_ready: if send and i != len(data): - yield dut.p.i_valid.eq(1) - yield dut.p.i_data.eq(data[i]) + yield dut.p.valid_i.eq(1) + yield dut.p.data_i.eq(data[i]) i += 1 else: - yield dut.p.i_valid.eq(0) + yield dut.p.valid_i.eq(0) yield - o_n_valid = yield dut.n.o_valid - i_n_ready = yield dut.n.i_ready + o_n_valid = yield dut.n.valid_o + i_n_ready = yield dut.n.ready_i_test if o_n_valid and i_n_ready: - o_data = yield dut.n.o_data - assert o_data == data[o] + 2, "%d-%d data %x not match %x\n" \ - % (i, o, o_data, data[o]) + data_o = yield dut.n.data_o + assert data_o == data[o] + 2, "%d-%d data %x not match %x\n" \ + % (i, o, data_o, data[o]) o += 1 if o == len(data): break +###################################################################### +# Test 2 and 4 +###################################################################### -class ExampleBufPipe2: - """ - connect these: ------|---------------| - v v - i_p_valid >>in pipe1 o_n_valid out>> i_p_valid >>in pipe2 - o_p_ready <>in pipe1 p_i_data out>> n_o_data >>in pipe2 +class ExampleBufPipe2(ControlBase): + """ Example of how to do chained pipeline stages. """ - def __init__(self): - self.pipe1 = ExampleBufPipe() - self.pipe2 = ExampleBufPipe() - - # input - self.p = PrevControl() - self.p.i_data = Signal(32) # >>in - comes in from the PREVIOUS stage - - # output - self.n = NextControl() - self.n.o_data = Signal(32) # out>> - goes out to the NEXT stage def elaborate(self, platform): - m = Module() - m.submodules.pipe1 = self.pipe1 - m.submodules.pipe2 = self.pipe2 + m = ControlBase.elaborate(self, platform) - # connect inter-pipe input/output valid/ready/data - m.d.comb += self.pipe1.connect_to_next(self.pipe2) + pipe1 = ExampleBufPipe() + pipe2 = ExampleBufPipe() - # inputs/outputs to the module: pipe1 connections here (LHS) - m.d.comb += self.pipe1.connect_in(self) + m.submodules.pipe1 = pipe1 + m.submodules.pipe2 = pipe2 - # now pipe2 connections (RHS) - m.d.comb += self.pipe2.connect_out(self) + m.d.comb += self.connect([pipe1, pipe2]) return m -class ExampleBufPipeChain2(BufferedPipeline): +###################################################################### +# Test 9 +###################################################################### + +class ExampleBufPipeChain2(BufferedHandshake): """ connects two stages together as a *single* combinatorial stage. """ def __init__(self): stage1 = ExampleStageCls() stage2 = ExampleStageCls() combined = StageChain([stage1, stage2]) - BufferedPipeline.__init__(self, combined) + BufferedHandshake.__init__(self, combined) def data_chain2(): @@ -316,34 +331,41 @@ def data_chain2(): return data -def test9_resultfn(o_data, expected, i, o): +def resultfn_9(data_o, expected, i, o): res = expected + 2 - assert o_data == res, \ - "%d-%d data %x not match %s\n" \ - % (i, o, o_data, repr(expected)) + assert data_o == res, \ + "%d-%d received data %x not match expected %x\n" \ + % (i, o, data_o, res) + +###################################################################### +# Test 6 and 10 +###################################################################### -class SetLessThan: +class SetLessThan(Elaboratable): def __init__(self, width, signed): - self.src1 = Signal((width, signed)) - self.src2 = Signal((width, signed)) - self.output = Signal(width) + self.m = Module() + self.src1 = Signal((width, signed), name="src1") + self.src2 = Signal((width, signed), name="src2") + self.output = Signal(width, name="out") def elaborate(self, platform): - m = Module() - m.d.comb += self.output.eq(Mux(self.src1 < self.src2, 1, 0)) - return m + self.m.d.comb += self.output.eq(Mux(self.src1 < self.src2, 1, 0)) + return self.m -class LTStage: +class LTStage(StageCls): + """ module-based stage example + """ def __init__(self): self.slt = SetLessThan(16, True) - def ispec(self): - return (Signal(16), Signal(16)) + def ispec(self, name): + return (Signal(16, name="%s_sig1" % name), + Signal(16, name="%s_sig2" % name)) - def ospec(self): - return Signal(16) + def ospec(self, name): + return Signal(16, "%s_out" % name) def setup(self, m, i): self.o = Signal(16) @@ -356,7 +378,13 @@ class LTStage: return self.o -class LTStageDerived(SetLessThan): +class LTStageDerived(SetLessThan, StageCls): + """ special version of a nmigen module where the module is also a stage + + shows that you don't actually need to combinatorially connect + to the outputs, or add the module as a submodule: just return + the module output parameter(s) from the Stage.process() function + """ def __init__(self): SetLessThan.__init__(self, 16, True) @@ -377,7 +405,7 @@ class LTStageDerived(SetLessThan): class ExampleLTPipeline(UnbufferedPipeline): - """ an example of how to use the combinatorial pipeline. + """ an example of how to use the unbuffered pipeline. """ def __init__(self): @@ -385,23 +413,27 @@ class ExampleLTPipeline(UnbufferedPipeline): UnbufferedPipeline.__init__(self, stage) -class ExampleLTBufferedPipeDerived(BufferedPipeline): - """ an example of how to use the combinatorial pipeline. +class ExampleLTBufferedPipeDerived(BufferedHandshake): + """ an example of how to use the buffered pipeline. """ def __init__(self): stage = LTStageDerived() - BufferedPipeline.__init__(self, stage) + BufferedHandshake.__init__(self, stage) -def test6_resultfn(o_data, expected, i, o): +def resultfn_6(data_o, expected, i, o): res = 1 if expected[0] < expected[1] else 0 - assert o_data == res, \ + assert data_o == res, \ "%d-%d data %x not match %s\n" \ - % (i, o, o_data, repr(expected)) + % (i, o, data_o, repr(expected)) -class ExampleAddRecordStage: +###################################################################### +# Test 7 +###################################################################### + +class ExampleAddRecordStage(StageCls): """ example use of a Record """ @@ -421,8 +453,11 @@ class ExampleAddRecordStage: return {'src1': i.src1 + 1, 'src2': i.src2 + 1} +###################################################################### +# Test 11 +###################################################################### -class ExampleAddRecordPlaceHolderStage: +class ExampleAddRecordPlaceHolderStage(StageCls): """ example use of a Record, with a placeholder as the processing result """ @@ -444,6 +479,8 @@ class ExampleAddRecordPlaceHolderStage: o.src2 = i.src2 + 1 return o + +# a dummy class that may have stuff assigned to instances once created class PlaceHolder: pass @@ -456,11 +493,11 @@ class ExampleAddRecordPipe(UnbufferedPipeline): UnbufferedPipeline.__init__(self, stage) -def test7_resultfn(o_data, expected, i, o): +def resultfn_7(data_o, expected, i, o): res = (expected['src1'] + 1, expected['src2'] + 1) - assert o_data['src1'] == res[0] and o_data['src2'] == res[1], \ + assert data_o['src1'] == res[0] and data_o['src2'] == res[1], \ "%d-%d data %s not match %s\n" \ - % (i, o, repr(o_data), repr(expected)) + % (i, o, repr(data_o), repr(expected)) class ExampleAddRecordPlaceHolderPipe(UnbufferedPipeline): @@ -472,12 +509,17 @@ class ExampleAddRecordPlaceHolderPipe(UnbufferedPipeline): UnbufferedPipeline.__init__(self, stage) -def test11_resultfn(o_data, expected, i, o): +def resultfn_test11(data_o, expected, i, o): res1 = expected.src1 + 1 res2 = expected.src2 + 1 - assert o_data['src1'] == res1 and o_data['src2'] == res2, \ + assert data_o['src1'] == res1 and data_o['src2'] == res2, \ "%d-%d data %s not match %s\n" \ - % (i, o, repr(o_data), repr(expected)) + % (i, o, repr(data_o), repr(expected)) + + +###################################################################### +# Test 8 +###################################################################### class Example2OpClass: @@ -493,7 +535,7 @@ class Example2OpClass: return [self.op1.eq(i.op1), self.op2.eq(i.op2)] -class ExampleAddClassStage: +class ExampleAddClassStage(StageCls): """ an example of how to use the buffered pipeline, as a class instance """ @@ -506,7 +548,7 @@ class ExampleAddClassStage: """ returns an output signal which will happen to contain the sum of the two inputs """ - return Signal(16) + return Signal(16, name="add2_out") def process(self, i): """ process the input data (sums the values in the tuple) and returns it @@ -514,13 +556,13 @@ class ExampleAddClassStage: return i.op1 + i.op2 -class ExampleBufPipeAddClass(BufferedPipeline): +class ExampleBufPipeAddClass(BufferedHandshake): """ an example of how to use the buffered pipeline, using a class instance """ def __init__(self): addstage = ExampleAddClassStage() - BufferedPipeline.__init__(self, addstage) + BufferedHandshake.__init__(self, addstage) class TestInputAdd: @@ -534,11 +576,11 @@ class TestInputAdd: self.op2 = op2 -def test8_resultfn(o_data, expected, i, o): +def resultfn_8(data_o, expected, i, o): res = expected.op1 + expected.op2 # these are a TestInputAdd instance - assert o_data == res, \ - "%d-%d data %x not match %s\n" \ - % (i, o, o_data, repr(expected)) + assert data_o == res, \ + "%d-%d data %s res %x not match %s\n" \ + % (i, o, repr(data_o), res, repr(expected)) def data_2op(): data = [] @@ -546,125 +588,477 @@ def data_2op(): data.append(TestInputAdd(randint(0, 1<<16-1), randint(0, 1<<16-1))) return data -class InputPriorityArbiter: - def __init__(self, pipe, num_rows): - self.pipe = pipe - self.num_rows = num_rows - self.mmax = int(log(self.num_rows) / log(2)) - self.mid = Signal(self.mmax, reset_less=True) # multiplex id - self.active = Signal(reset_less=True) + +###################################################################### +# Test 12 +###################################################################### + +class ExampleStageDelayCls(StageCls, Elaboratable): + """ an example of how to use the buffered pipeline, in a static class + fashion + """ + + def __init__(self, valid_trigger=2): + self.count = Signal(2) + self.valid_trigger = valid_trigger + + def ispec(self): + return Signal(16, name="example_input_signal") + + def ospec(self): + return Signal(16, name="example_output_signal") + + @property + def d_ready(self): + """ data is ready to be accepted when this is true + """ + return (self.count == 1)# | (self.count == 3) + return Const(1) + + def d_valid(self, ready_i): + """ data is valid at output when this is true + """ + return self.count == self.valid_trigger + return Const(1) + + def process(self, i): + """ process the input data and returns it (adds 1) + """ + return i + 1 def elaborate(self, platform): m = Module() + m.d.sync += self.count.eq(self.count + 1) + return m + - assert len(self.pipe.p) == self.num_rows, \ - "must declare input to be same size" - pe = PriorityEncoder(self.num_rows) - m.submodules.selector = pe - - # connect priority encoder - in_ready = [] - for i in range(self.num_rows): - p_i_valid = Signal(reset_less=True) - m.d.comb += p_i_valid.eq(self.pipe[i].i_valid_logic()) - in_ready.append(p_i_valid) - m.d.comb += pe.i.eq(Cat(*in_ready)) # array of input "valids" - m.d.comb += self.active.eq(~pe.n) # encoder active (one input valid) - m.d.comb += self.mid.eq(pe.o) # output one active input +class ExampleBufDelayedPipe(BufferedHandshake): + def __init__(self): + stage = ExampleStageDelayCls(valid_trigger=2) + BufferedHandshake.__init__(self, stage, stage_ctl=True) + + def elaborate(self, platform): + m = BufferedHandshake.elaborate(self, platform) + m.submodules.stage = self.stage return m - def ports(self): - return [self.mid, self.active] +def data_chain1(): + data = [] + for i in range(num_tests): + data.append(1<<((i*3)%15)) + #data.append(randint(0, 1<<16-2)) + #print (hex(data[-1])) + return data + + +def resultfn_12(data_o, expected, i, o): + res = expected + 1 + assert data_o == res, \ + "%d-%d data %x not match %x\n" \ + % (i, o, data_o, res) -class PriorityUnbufferedPipeline(UnbufferedPipeline): - def __init__(self, stage, p_len=4): - p_mux = InputPriorityArbiter(self, p_len) - UnbufferedPipeline.__init__(stage, p_len=p_len, p_mux=p_mux) + +###################################################################### +# Test 13 +###################################################################### + +class ExampleUnBufDelayedPipe(BufferedHandshake): + + def __init__(self): + stage = ExampleStageDelayCls(valid_trigger=3) + BufferedHandshake.__init__(self, stage, stage_ctl=True) def elaborate(self, platform): - m = Module() + m = BufferedHandshake.elaborate(self, platform) + m.submodules.stage = self.stage + return m + +###################################################################### +# Test 15 +###################################################################### + +class ExampleBufModeAdd1Pipe(SimpleHandshake): + + def __init__(self): + stage = ExampleStageCls() + SimpleHandshake.__init__(self, stage) + + +###################################################################### +# Test 16 +###################################################################### + +class ExampleBufModeUnBufPipe(ControlBase): + + def elaborate(self, platform): + m = ControlBase.elaborate(self, platform) + + pipe1 = ExampleBufModeAdd1Pipe() + pipe2 = ExampleBufAdd1Pipe() + + m.submodules.pipe1 = pipe1 + m.submodules.pipe2 = pipe2 + + m.d.comb += self.connect([pipe1, pipe2]) + + return m + +###################################################################### +# Test 17 +###################################################################### + +class ExampleUnBufAdd1Pipe2(UnbufferedPipeline2): + + def __init__(self): + stage = ExampleStageCls() + UnbufferedPipeline2.__init__(self, stage) + + +###################################################################### +# Test 18 +###################################################################### + +class PassThroughTest(PassThroughHandshake): + + def iospecfn(self): + return Signal(16, "out") + + def __init__(self): + stage = PassThroughStage(self.iospecfn) + PassThroughHandshake.__init__(self, stage) + +def resultfn_identical(data_o, expected, i, o): + res = expected + assert data_o == res, \ + "%d-%d data %x not match %x\n" \ + % (i, o, data_o, res) + + +###################################################################### +# Test 19 +###################################################################### + +class ExamplePassAdd1Pipe(PassThroughHandshake): + + def __init__(self): + stage = ExampleStageCls() + PassThroughHandshake.__init__(self, stage) + + +class ExampleBufPassThruPipe(ControlBase): + + def elaborate(self, platform): + m = ControlBase.elaborate(self, platform) + + # XXX currently fails: any other permutation works fine. + # p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok + # also fails using UnbufferedPipeline as well + pipe1 = ExampleBufModeAdd1Pipe() + pipe2 = ExamplePassAdd1Pipe() + + m.submodules.pipe1 = pipe1 + m.submodules.pipe2 = pipe2 + + m.d.comb += self.connect([pipe1, pipe2]) + + return m + + +###################################################################### +# Test 20 +###################################################################### + +def iospecfn(): + return Signal(16, name="d_in") + +class FIFOTest16(FIFOControl): + + def __init__(self): + stage = PassThroughStage(iospecfn) + FIFOControl.__init__(self, 2, stage) + + +###################################################################### +# Test 21 +###################################################################### + +class ExampleFIFOPassThruPipe1(ControlBase): + + def elaborate(self, platform): + m = ControlBase.elaborate(self, platform) + + pipe1 = FIFOTest16() + pipe2 = FIFOTest16() + pipe3 = ExamplePassAdd1Pipe() + + m.submodules.pipe1 = pipe1 + m.submodules.pipe2 = pipe2 + m.submodules.pipe3 = pipe3 + + m.d.comb += self.connect([pipe1, pipe2, pipe3]) + + return m + + +###################################################################### +# Test 22 +###################################################################### + +class Example2OpRecord(RecordObject): + def __init__(self): + RecordObject.__init__(self) + self.op1 = Signal(16) + self.op2 = Signal(16) + + +class ExampleAddRecordObjectStage(StageCls): + + def ispec(self): + """ returns an instance of an Example2OpRecord. + """ + return Example2OpRecord() + + def ospec(self): + """ returns an output signal which will happen to contain the sum + of the two inputs + """ + return Signal(16) + + def process(self, i): + """ process the input data (sums the values in the tuple) and returns it + """ + return i.op1 + i.op2 + + +class ExampleRecordHandshakeAddClass(SimpleHandshake): + + def __init__(self): + addstage = ExampleAddRecordObjectStage() + SimpleHandshake.__init__(self, stage=addstage) + + +###################################################################### +# Test 23 +###################################################################### + +def iospecfnrecord(): + return Example2OpRecord() + +class FIFOTestRecordControl(FIFOControl): + + def __init__(self): + stage = PassThroughStage(iospecfnrecord) + FIFOControl.__init__(self, 2, stage) + + +class ExampleFIFORecordObjectPipe(ControlBase): + + def elaborate(self, platform): + m = ControlBase.elaborate(self, platform) + + pipe1 = FIFOTestRecordControl() + pipe2 = ExampleRecordHandshakeAddClass() - pe = PriorityEncoder(self.num_rows) - m.submodules.selector = pe - m.submodules.out_op = self.out_op - m.submodules += self.rs - - # connect priority encoder - in_ready = [] - for i in range(self.num_rows): - in_ready.append(self.rs[i].ready) - m.d.comb += pe.i.eq(Cat(*in_ready)) - - active = Signal(reset_less=True) - out_en = Signal(reset_less=True) - m.d.comb += active.eq(~pe.n) # encoder active - m.d.comb += out_en.eq(active & self.out_op.trigger) - - # encoder active: ack relevant input, record MID, pass output - with m.If(out_en): - rs = self.rs[pe.o] - m.d.sync += self.mid.eq(pe.o) - m.d.sync += rs.ack.eq(0) - m.d.sync += self.out_op.stb.eq(0) - for j in range(self.num_ops): - m.d.sync += self.out_op.v[j].eq(rs.out_op[j]) - with m.Else(): - m.d.sync += self.out_op.stb.eq(1) - # acks all default to zero - for i in range(self.num_rows): - m.d.sync += self.rs[i].ack.eq(1) + m.submodules.pipe1 = pipe1 + m.submodules.pipe2 = pipe2 + + m.d.comb += self.connect([pipe1, pipe2]) return m - def ports(self): - res = [] - for i in range(self.num_rows): - inop = self.rs[i] - res += inop.in_op + [inop.stb] - return self.out_op.ports() + res + [self.mid] + +###################################################################### +# Test 24 +###################################################################### + +class FIFOTestRecordAddStageControl(FIFOControl): + + def __init__(self): + stage = ExampleAddRecordObjectStage() + FIFOControl.__init__(self, 2, stage) + + + +###################################################################### +# Test 25 +###################################################################### + +class FIFOTestAdd16(FIFOControl): + + def __init__(self): + stage = ExampleStageCls() + FIFOControl.__init__(self, 2, stage) + + +class ExampleFIFOAdd2Pipe(ControlBase): + + def elaborate(self, platform): + m = ControlBase.elaborate(self, platform) + + pipe1 = FIFOTestAdd16() + pipe2 = FIFOTestAdd16() + + m.submodules.pipe1 = pipe1 + m.submodules.pipe2 = pipe2 + + m.d.comb += self.connect([pipe1, pipe2]) + + return m + + +###################################################################### +# Test 26 +###################################################################### + +def iospecfn24(): + return (Signal(16, name="src1"), Signal(16, name="src2")) + +class FIFOTest2x16(FIFOControl): + + def __init__(self): + stage = PassThroughStage(iospecfn2) + FIFOControl.__init__(self, 2, stage) + + +###################################################################### +# Test 997 +###################################################################### + +class ExampleBufPassThruPipe2(ControlBase): + + def elaborate(self, platform): + m = ControlBase.elaborate(self, platform) + + # XXX currently fails: any other permutation works fine. + # p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok + # also fails using UnbufferedPipeline as well + #pipe1 = ExampleUnBufAdd1Pipe() + #pipe2 = ExampleBufAdd1Pipe() + pipe1 = ExampleBufAdd1Pipe() + pipe2 = ExamplePassAdd1Pipe() + + m.submodules.pipe1 = pipe1 + m.submodules.pipe2 = pipe2 + + m.d.comb += self.connect([pipe1, pipe2]) + + return m + + +###################################################################### +# Test 998 +###################################################################### + +class ExampleBufPipe3(ControlBase): + """ Example of how to do delayed pipeline, where the stage signals + whether it is ready. + """ + + def elaborate(self, platform): + m = ControlBase.elaborate(self, platform) + + pipe1 = ExampleBufDelayedPipe() + pipe2 = ExampleBufPipe() + + m.submodules.pipe1 = pipe1 + m.submodules.pipe2 = pipe2 + + m.d.comb += self.connect([pipe1, pipe2]) + + return m + +###################################################################### +# Test 999 - XXX FAILS +# http://bugs.libre-riscv.org/show_bug.cgi?id=57 +###################################################################### + +class ExampleBufAdd1Pipe(BufferedHandshake): + + def __init__(self): + stage = ExampleStageCls() + BufferedHandshake.__init__(self, stage) + + +class ExampleUnBufAdd1Pipe(UnbufferedPipeline): + + def __init__(self): + stage = ExampleStageCls() + UnbufferedPipeline.__init__(self, stage) + + +class ExampleBufUnBufPipe(ControlBase): + + def elaborate(self, platform): + m = ControlBase.elaborate(self, platform) + + # XXX currently fails: any other permutation works fine. + # p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok + # also fails using UnbufferedPipeline as well + #pipe1 = ExampleUnBufAdd1Pipe() + #pipe2 = ExampleBufAdd1Pipe() + pipe1 = ExampleBufAdd1Pipe() + pipe2 = ExampleUnBufAdd1Pipe() + + m.submodules.pipe1 = pipe1 + m.submodules.pipe2 = pipe2 + + m.d.comb += self.connect([pipe1, pipe2]) + + return m +###################################################################### +# Unit Tests +###################################################################### -num_tests = 100 +num_tests = 10 if __name__ == '__main__': - print ("test 1") - dut = ExampleBufPipe() - run_simulation(dut, testbench(dut), vcd_name="test_bufpipe.vcd") + if False: + print ("test 1") + dut = ExampleBufPipe() + run_simulation(dut, tbench(dut), vcd_name="test_bufpipe.vcd") + + print ("test 2") + dut = ExampleBufPipe2() + run_simulation(dut, tbench2(dut), vcd_name="test_bufpipe2.vcd") + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] + vl = rtlil.convert(dut, ports=ports) + with open("test_bufpipe2.il", "w") as f: + f.write(vl) - print ("test 2") - dut = ExampleBufPipe2() - run_simulation(dut, testbench2(dut), vcd_name="test_bufpipe2.vcd") print ("test 3") dut = ExampleBufPipe() - test = Test3(dut, test3_resultfn) + test = Test3(dut, resultfn_3) run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe3.vcd") print ("test 3.5") dut = ExamplePipeline() - test = Test3(dut, test3_resultfn) + test = Test3(dut, resultfn_3) run_simulation(dut, [test.send, test.rcv], vcd_name="test_combpipe3.vcd") print ("test 4") dut = ExampleBufPipe2() - run_simulation(dut, testbench4(dut), vcd_name="test_bufpipe4.vcd") + run_simulation(dut, tbench4(dut), vcd_name="test_bufpipe4.vcd") print ("test 5") dut = ExampleBufPipeAdd() - test = Test5(dut, test5_resultfn) + test = Test5(dut, resultfn_5, stage_ctl=True) run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe5.vcd") print ("test 6") dut = ExampleLTPipeline() - test = Test5(dut, test6_resultfn) + test = Test5(dut, resultfn_6) run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltcomb6.vcd") - ports = [dut.p[0].i_valid, dut.n[0].i_ready, - dut.n[0].o_valid, dut.p[0].o_ready] + \ - list(dut.p[0].i_data) + [dut.n[0].o_data] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + list(dut.p.data_i) + [dut.n.data_o] vl = rtlil.convert(dut, ports=ports) with open("test_ltcomb_pipe.il", "w") as f: f.write(vl) @@ -672,40 +1066,39 @@ if __name__ == '__main__': print ("test 7") dut = ExampleAddRecordPipe() data=data_dict() - test = Test5(dut, test7_resultfn, data=data) - run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord.vcd") - - ports = [dut.p[0].i_valid, dut.n[0].i_ready, - dut.n[0].o_valid, dut.p[0].o_ready, - dut.p[0].i_data.src1, dut.p[0].i_data.src2, - dut.n[0].o_data.src1, dut.n[0].o_data.src2] + test = Test5(dut, resultfn_7, data=data) + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o, + dut.p.data_i.src1, dut.p.data_i.src2, + dut.n.data_o.src1, dut.n.data_o.src2] vl = rtlil.convert(dut, ports=ports) with open("test_recordcomb_pipe.il", "w") as f: f.write(vl) + run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord.vcd") print ("test 8") dut = ExampleBufPipeAddClass() data=data_2op() - test = Test5(dut, test8_resultfn, data=data) + test = Test5(dut, resultfn_8, data=data) run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe8.vcd") print ("test 9") dut = ExampleBufPipeChain2() - ports = [dut.p[0].i_valid, dut.n[0].i_ready, - dut.n[0].o_valid, dut.p[0].o_ready] + \ - [dut.p[0].i_data] + [dut.n[0].o_data] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] vl = rtlil.convert(dut, ports=ports) with open("test_bufpipechain2.il", "w") as f: f.write(vl) data = data_chain2() - test = Test5(dut, test9_resultfn, data=data) + test = Test5(dut, resultfn_9, data=data) run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipechain2.vcd") print ("test 10") dut = ExampleLTBufferedPipeDerived() - test = Test5(dut, test6_resultfn) + test = Test5(dut, resultfn_6) run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltbufpipe10.vcd") vl = rtlil.convert(dut, ports=ports) with open("test_ltbufpipe10.il", "w") as f: @@ -714,7 +1107,202 @@ if __name__ == '__main__': print ("test 11") dut = ExampleAddRecordPlaceHolderPipe() data=data_placeholder() - test = Test5(dut, test11_resultfn, data=data) + test = Test5(dut, resultfn_test11, data=data) run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord.vcd") + print ("test 12") + dut = ExampleBufDelayedPipe() + data = data_chain1() + test = Test5(dut, resultfn_12, data=data) + run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe12.vcd") + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] + vl = rtlil.convert(dut, ports=ports) + with open("test_bufpipe12.il", "w") as f: + f.write(vl) + + print ("test 13") + dut = ExampleUnBufDelayedPipe() + data = data_chain1() + test = Test5(dut, resultfn_12, data=data) + run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe13.vcd") + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] + vl = rtlil.convert(dut, ports=ports) + with open("test_unbufpipe13.il", "w") as f: + f.write(vl) + + print ("test 15") + dut = ExampleBufModeAdd1Pipe() + data = data_chain1() + test = Test5(dut, resultfn_12, data=data) + run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf15.vcd") + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] + vl = rtlil.convert(dut, ports=ports) + with open("test_bufunbuf15.il", "w") as f: + f.write(vl) + + print ("test 16") + dut = ExampleBufModeUnBufPipe() + data = data_chain1() + test = Test5(dut, resultfn_9, data=data) + run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf16.vcd") + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] + vl = rtlil.convert(dut, ports=ports) + with open("test_bufunbuf16.il", "w") as f: + f.write(vl) + + print ("test 17") + dut = ExampleUnBufAdd1Pipe2() + data = data_chain1() + test = Test5(dut, resultfn_12, data=data) + run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe17.vcd") + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] + vl = rtlil.convert(dut, ports=ports) + with open("test_unbufpipe17.il", "w") as f: + f.write(vl) + + print ("test 18") + dut = PassThroughTest() + data = data_chain1() + test = Test5(dut, resultfn_identical, data=data) + run_simulation(dut, [test.send, test.rcv], vcd_name="test_passthru18.vcd") + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] + vl = rtlil.convert(dut, ports=ports) + with open("test_passthru18.il", "w") as f: + f.write(vl) + + print ("test 19") + dut = ExampleBufPassThruPipe() + data = data_chain1() + test = Test5(dut, resultfn_9, data=data) + run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass19.vcd") + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] + vl = rtlil.convert(dut, ports=ports) + with open("test_bufpass19.il", "w") as f: + f.write(vl) + + print ("test 20") + dut = FIFOTest16() + data = data_chain1() + test = Test5(dut, resultfn_identical, data=data) + run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifo20.vcd") + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] + vl = rtlil.convert(dut, ports=ports) + with open("test_fifo20.il", "w") as f: + f.write(vl) + + print ("test 21") + dut = ExampleFIFOPassThruPipe1() + data = data_chain1() + test = Test5(dut, resultfn_12, data=data) + run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifopass21.vcd") + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] + vl = rtlil.convert(dut, ports=ports) + with open("test_fifopass21.il", "w") as f: + f.write(vl) + + print ("test 22") + dut = ExampleRecordHandshakeAddClass() + data=data_2op() + test = Test5(dut, resultfn_8, data=data) + run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord22.vcd") + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i.op1, dut.p.data_i.op2] + \ + [dut.n.data_o] + vl = rtlil.convert(dut, ports=ports) + with open("test_addrecord22.il", "w") as f: + f.write(vl) + + print ("test 23") + dut = ExampleFIFORecordObjectPipe() + data=data_2op() + test = Test5(dut, resultfn_8, data=data) + run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord23.vcd") + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i.op1, dut.p.data_i.op2] + \ + [dut.n.data_o] + vl = rtlil.convert(dut, ports=ports) + with open("test_addrecord23.il", "w") as f: + f.write(vl) + + print ("test 24") + dut = FIFOTestRecordAddStageControl() + data=data_2op() + test = Test5(dut, resultfn_8, data=data) + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i.op1, dut.p.data_i.op2] + \ + [dut.n.data_o] + vl = rtlil.convert(dut, ports=ports) + with open("test_addrecord24.il", "w") as f: + f.write(vl) + run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord24.vcd") + + print ("test 25") + dut = ExampleFIFOAdd2Pipe() + data = data_chain1() + test = Test5(dut, resultfn_9, data=data) + run_simulation(dut, [test.send, test.rcv], vcd_name="test_add2pipe25.vcd") + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] + vl = rtlil.convert(dut, ports=ports) + with open("test_add2pipe25.il", "w") as f: + f.write(vl) + + print ("test 997") + dut = ExampleBufPassThruPipe2() + data = data_chain1() + test = Test5(dut, resultfn_9, data=data) + run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass997.vcd") + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] + vl = rtlil.convert(dut, ports=ports) + with open("test_bufpass997.il", "w") as f: + f.write(vl) + + print ("test 998 (fails, bug)") + dut = ExampleBufPipe3() + data = data_chain1() + test = Test5(dut, resultfn_9, data=data) + run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe14.vcd") + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] + vl = rtlil.convert(dut, ports=ports) + with open("test_bufpipe14.il", "w") as f: + f.write(vl) + + print ("test 999 (expected to fail, which is a bug)") + dut = ExampleBufUnBufPipe() + data = data_chain1() + test = Test5(dut, resultfn_9, data=data) + run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf999.vcd") + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] + vl = rtlil.convert(dut, ports=ports) + with open("test_bufunbuf999.il", "w") as f: + f.write(vl) +