X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Ftest_buf_pipe.py;h=37f2b31f8b0a3ce38d2067b569a28344e6ab7fd9;hb=6bff1a997f3846872cf489c24b5c01426c4dc97c;hp=ee1734e88a16c31c09ca25104c8b0087084bfe2a;hpb=2814d7626846b954214132fd4a9b63e5c9b0e9d7;p=ieee754fpu.git diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py index ee1734e8..37f2b31f 100644 --- a/src/add/test_buf_pipe.py +++ b/src/add/test_buf_pipe.py @@ -14,7 +14,7 @@ """ -from nmigen import Module, Signal, Mux, Const +from nmigen import Module, Signal, Mux, Const, Elaboratable from nmigen.hdl.rec import Record from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil @@ -37,41 +37,41 @@ from random import randint, seed def check_o_n_valid(dut, val): - o_n_valid = yield dut.n.o_valid + o_n_valid = yield dut.n.valid_o assert o_n_valid == val def check_o_n_valid2(dut, val): - o_n_valid = yield dut.n.o_valid + o_n_valid = yield dut.n.valid_o assert o_n_valid == val def tbench(dut): #yield dut.i_p_rst.eq(1) - yield dut.n.i_ready.eq(0) - #yield dut.p.o_ready.eq(0) + yield dut.n.ready_i.eq(0) + #yield dut.p.ready_o.eq(0) yield yield #yield dut.i_p_rst.eq(0) - yield dut.n.i_ready.eq(1) - yield dut.p.i_data.eq(5) - yield dut.p.i_valid.eq(1) + yield dut.n.ready_i.eq(1) + yield dut.p.data_i.eq(5) + yield dut.p.valid_i.eq(1) yield - yield dut.p.i_data.eq(7) + yield dut.p.data_i.eq(7) yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed yield yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt - yield dut.p.i_data.eq(2) + yield dut.p.data_i.eq(2) yield - yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready) - yield dut.p.i_data.eq(9) + yield dut.n.ready_i.eq(0) # begin going into "stall" (next stage says ready) + yield dut.p.data_i.eq(9) yield - yield dut.p.i_valid.eq(0) - yield dut.p.i_data.eq(12) + yield dut.p.valid_i.eq(0) + yield dut.p.data_i.eq(12) yield - yield dut.p.i_data.eq(32) - yield dut.n.i_ready.eq(1) + yield dut.p.data_i.eq(32) + yield dut.n.ready_i.eq(1) yield yield from check_o_n_valid(dut, 1) # buffer still needs to output yield @@ -83,32 +83,32 @@ def tbench(dut): def tbench2(dut): #yield dut.p.i_rst.eq(1) - yield dut.n.i_ready.eq(0) - #yield dut.p.o_ready.eq(0) + yield dut.n.ready_i.eq(0) + #yield dut.p.ready_o.eq(0) yield yield #yield dut.p.i_rst.eq(0) - yield dut.n.i_ready.eq(1) - yield dut.p.i_data.eq(5) - yield dut.p.i_valid.eq(1) + yield dut.n.ready_i.eq(1) + yield dut.p.data_i.eq(5) + yield dut.p.valid_i.eq(1) yield - yield dut.p.i_data.eq(7) + yield dut.p.data_i.eq(7) yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks yield yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks - yield dut.p.i_data.eq(2) + yield dut.p.data_i.eq(2) yield yield from check_o_n_valid2(dut, 1) # ok *now* i_p_valid effect is felt - yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready) - yield dut.p.i_data.eq(9) + yield dut.n.ready_i.eq(0) # begin going into "stall" (next stage says ready) + yield dut.p.data_i.eq(9) yield - yield dut.p.i_valid.eq(0) - yield dut.p.i_data.eq(12) + yield dut.p.valid_i.eq(0) + yield dut.p.data_i.eq(12) yield - yield dut.p.i_data.eq(32) - yield dut.n.i_ready.eq(1) + yield dut.p.data_i.eq(32) + yield dut.n.ready_i.eq(1) yield yield from check_o_n_valid2(dut, 1) # buffer still needs to output yield @@ -141,16 +141,16 @@ class Test3: send = True else: send = randint(0, send_range) != 0 - o_p_ready = yield self.dut.p.o_ready + o_p_ready = yield self.dut.p.ready_o if not o_p_ready: yield continue if send and self.i != len(self.data): - yield self.dut.p.i_valid.eq(1) - yield self.dut.p.i_data.eq(self.data[self.i]) + yield self.dut.p.valid_i.eq(1) + yield self.dut.p.data_i.eq(self.data[self.i]) self.i += 1 else: - yield self.dut.p.i_valid.eq(0) + yield self.dut.p.valid_i.eq(0) yield def rcv(self): @@ -158,22 +158,22 @@ class Test3: stall_range = randint(0, 3) for j in range(randint(1,10)): stall = randint(0, stall_range) != 0 - yield self.dut.n.i_ready.eq(stall) + yield self.dut.n.ready_i.eq(stall) yield - o_n_valid = yield self.dut.n.o_valid - i_n_ready = yield self.dut.n.i_ready_test + o_n_valid = yield self.dut.n.valid_o + i_n_ready = yield self.dut.n.ready_i_test if not o_n_valid or not i_n_ready: continue - o_data = yield self.dut.n.o_data - self.resultfn(o_data, self.data[self.o], self.i, self.o) + data_o = yield self.dut.n.data_o + self.resultfn(data_o, self.data[self.o], self.i, self.o) self.o += 1 if self.o == len(self.data): break -def resultfn_3(o_data, expected, i, o): - assert o_data == expected + 1, \ +def resultfn_3(data_o, expected, i, o): + assert data_o == expected + 1, \ "%d-%d data %x not match %x\n" \ - % (i, o, o_data, expected) + % (i, o, data_o, expected) def data_placeholder(): data = [] @@ -215,17 +215,17 @@ class Test5: else: send = randint(0, send_range) != 0 #send = True - o_p_ready = yield self.dut.p.o_ready + o_p_ready = yield self.dut.p.ready_o if not o_p_ready: yield continue if send and self.i != len(self.data): - yield self.dut.p.i_valid.eq(1) + yield self.dut.p.valid_i.eq(1) for v in self.dut.set_input(self.data[self.i]): yield v self.i += 1 else: - yield self.dut.p.i_valid.eq(0) + yield self.dut.p.valid_i.eq(0) yield def rcv(self): @@ -234,29 +234,29 @@ class Test5: for j in range(randint(1,10)): ready = randint(0, stall_range) != 0 #ready = True - yield self.dut.n.i_ready.eq(ready) + yield self.dut.n.ready_i.eq(ready) yield - o_n_valid = yield self.dut.n.o_valid - i_n_ready = yield self.dut.n.i_ready_test + o_n_valid = yield self.dut.n.valid_o + i_n_ready = yield self.dut.n.ready_i_test if not o_n_valid or not i_n_ready: continue - if isinstance(self.dut.n.o_data, Record): - o_data = {} - dod = self.dut.n.o_data + if isinstance(self.dut.n.data_o, Record): + data_o = {} + dod = self.dut.n.data_o for k, v in dod.fields.items(): - o_data[k] = yield v + data_o[k] = yield v else: - o_data = yield self.dut.n.o_data - self.resultfn(o_data, self.data[self.o], self.i, self.o) + data_o = yield self.dut.n.data_o + self.resultfn(data_o, self.data[self.o], self.i, self.o) self.o += 1 if self.o == len(self.data): break -def resultfn_5(o_data, expected, i, o): +def resultfn_5(data_o, expected, i, o): res = expected[0] + expected[1] - assert o_data == res, \ + assert data_o == res, \ "%d-%d data %x not match %s\n" \ - % (i, o, o_data, repr(expected)) + % (i, o, data_o, repr(expected)) def tbench4(dut): data = [] @@ -268,22 +268,22 @@ def tbench4(dut): while True: stall = randint(0, 3) != 0 send = randint(0, 5) != 0 - yield dut.n.i_ready.eq(stall) - o_p_ready = yield dut.p.o_ready + yield dut.n.ready_i.eq(stall) + o_p_ready = yield dut.p.ready_o if o_p_ready: if send and i != len(data): - yield dut.p.i_valid.eq(1) - yield dut.p.i_data.eq(data[i]) + yield dut.p.valid_i.eq(1) + yield dut.p.data_i.eq(data[i]) i += 1 else: - yield dut.p.i_valid.eq(0) + yield dut.p.valid_i.eq(0) yield - o_n_valid = yield dut.n.o_valid - i_n_ready = yield dut.n.i_ready_test + o_n_valid = yield dut.n.valid_o + i_n_ready = yield dut.n.ready_i_test if o_n_valid and i_n_ready: - o_data = yield dut.n.o_data - assert o_data == data[o] + 2, "%d-%d data %x not match %x\n" \ - % (i, o, o_data, data[o]) + data_o = yield dut.n.data_o + assert data_o == data[o] + 2, "%d-%d data %x not match %x\n" \ + % (i, o, data_o, data[o]) o += 1 if o == len(data): break @@ -297,7 +297,7 @@ class ExampleBufPipe2(ControlBase): """ def elaborate(self, platform): - m = Module() + m = ControlBase.elaborate(self, platform) pipe1 = ExampleBufPipe() pipe2 = ExampleBufPipe() @@ -331,18 +331,18 @@ def data_chain2(): return data -def resultfn_9(o_data, expected, i, o): +def resultfn_9(data_o, expected, i, o): res = expected + 2 - assert o_data == res, \ + assert data_o == res, \ "%d-%d received data %x not match expected %x\n" \ - % (i, o, o_data, res) + % (i, o, data_o, res) ###################################################################### # Test 6 and 10 ###################################################################### -class SetLessThan: +class SetLessThan(Elaboratable): def __init__(self, width, signed): self.m = Module() self.src1 = Signal((width, signed), name="src1") @@ -360,11 +360,12 @@ class LTStage(StageCls): def __init__(self): self.slt = SetLessThan(16, True) - def ispec(self): - return (Signal(16, name="sig1"), Signal(16, "sig2")) + def ispec(self, name): + return (Signal(16, name="%s_sig1" % name), + Signal(16, name="%s_sig2" % name)) - def ospec(self): - return Signal(16, "out") + def ospec(self, name): + return Signal(16, "%s_out" % name) def setup(self, m, i): self.o = Signal(16) @@ -421,11 +422,11 @@ class ExampleLTBufferedPipeDerived(BufferedHandshake): BufferedHandshake.__init__(self, stage) -def resultfn_6(o_data, expected, i, o): +def resultfn_6(data_o, expected, i, o): res = 1 if expected[0] < expected[1] else 0 - assert o_data == res, \ + assert data_o == res, \ "%d-%d data %x not match %s\n" \ - % (i, o, o_data, repr(expected)) + % (i, o, data_o, repr(expected)) ###################################################################### @@ -479,6 +480,7 @@ class ExampleAddRecordPlaceHolderStage(StageCls): return o +# a dummy class that may have stuff assigned to instances once created class PlaceHolder: pass @@ -491,11 +493,11 @@ class ExampleAddRecordPipe(UnbufferedPipeline): UnbufferedPipeline.__init__(self, stage) -def resultfn_7(o_data, expected, i, o): +def resultfn_7(data_o, expected, i, o): res = (expected['src1'] + 1, expected['src2'] + 1) - assert o_data['src1'] == res[0] and o_data['src2'] == res[1], \ + assert data_o['src1'] == res[0] and data_o['src2'] == res[1], \ "%d-%d data %s not match %s\n" \ - % (i, o, repr(o_data), repr(expected)) + % (i, o, repr(data_o), repr(expected)) class ExampleAddRecordPlaceHolderPipe(UnbufferedPipeline): @@ -507,12 +509,12 @@ class ExampleAddRecordPlaceHolderPipe(UnbufferedPipeline): UnbufferedPipeline.__init__(self, stage) -def resultfn_test11(o_data, expected, i, o): +def resultfn_test11(data_o, expected, i, o): res1 = expected.src1 + 1 res2 = expected.src2 + 1 - assert o_data['src1'] == res1 and o_data['src2'] == res2, \ + assert data_o['src1'] == res1 and data_o['src2'] == res2, \ "%d-%d data %s not match %s\n" \ - % (i, o, repr(o_data), repr(expected)) + % (i, o, repr(data_o), repr(expected)) ###################################################################### @@ -546,7 +548,7 @@ class ExampleAddClassStage(StageCls): """ returns an output signal which will happen to contain the sum of the two inputs """ - return Signal(16) + return Signal(16, name="add2_out") def process(self, i): """ process the input data (sums the values in the tuple) and returns it @@ -574,11 +576,11 @@ class TestInputAdd: self.op2 = op2 -def resultfn_8(o_data, expected, i, o): +def resultfn_8(data_o, expected, i, o): res = expected.op1 + expected.op2 # these are a TestInputAdd instance - assert o_data == res, \ + assert data_o == res, \ "%d-%d data %s res %x not match %s\n" \ - % (i, o, repr(o_data), res, repr(expected)) + % (i, o, repr(data_o), res, repr(expected)) def data_2op(): data = [] @@ -591,7 +593,7 @@ def data_2op(): # Test 12 ###################################################################### -class ExampleStageDelayCls(StageCls): +class ExampleStageDelayCls(StageCls, Elaboratable): """ an example of how to use the buffered pipeline, in a static class fashion """ @@ -613,7 +615,7 @@ class ExampleStageDelayCls(StageCls): return (self.count == 1)# | (self.count == 3) return Const(1) - def d_valid(self, i_ready): + def d_valid(self, ready_i): """ data is valid at output when this is true """ return self.count == self.valid_trigger @@ -651,11 +653,11 @@ def data_chain1(): return data -def resultfn_12(o_data, expected, i, o): +def resultfn_12(data_o, expected, i, o): res = expected + 1 - assert o_data == res, \ + assert data_o == res, \ "%d-%d data %x not match %x\n" \ - % (i, o, o_data, res) + % (i, o, data_o, res) ###################################################################### @@ -691,7 +693,7 @@ class ExampleBufModeAdd1Pipe(SimpleHandshake): class ExampleBufModeUnBufPipe(ControlBase): def elaborate(self, platform): - m = ControlBase._elaborate(self, platform) + m = ControlBase.elaborate(self, platform) pipe1 = ExampleBufModeAdd1Pipe() pipe2 = ExampleBufAdd1Pipe() @@ -727,11 +729,11 @@ class PassThroughTest(PassThroughHandshake): stage = PassThroughStage(self.iospecfn) PassThroughHandshake.__init__(self, stage) -def resultfn_identical(o_data, expected, i, o): +def resultfn_identical(data_o, expected, i, o): res = expected - assert o_data == res, \ + assert data_o == res, \ "%d-%d data %x not match %x\n" \ - % (i, o, o_data, res) + % (i, o, data_o, res) ###################################################################### @@ -748,7 +750,7 @@ class ExamplePassAdd1Pipe(PassThroughHandshake): class ExampleBufPassThruPipe(ControlBase): def elaborate(self, platform): - m = ControlBase._elaborate(self, platform) + m = ControlBase.elaborate(self, platform) # XXX currently fails: any other permutation works fine. # p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok @@ -785,15 +787,17 @@ class FIFOTest16(FIFOControl): class ExampleFIFOPassThruPipe1(ControlBase): def elaborate(self, platform): - m = ControlBase._elaborate(self, platform) + m = ControlBase.elaborate(self, platform) pipe1 = FIFOTest16() - pipe2 = ExamplePassAdd1Pipe() + pipe2 = FIFOTest16() + pipe3 = ExamplePassAdd1Pipe() m.submodules.pipe1 = pipe1 m.submodules.pipe2 = pipe2 + m.submodules.pipe3 = pipe3 - m.d.comb += self.connect([pipe1, pipe2]) + m.d.comb += self.connect([pipe1, pipe2, pipe3]) return m @@ -852,7 +856,7 @@ class FIFOTestRecordControl(FIFOControl): class ExampleFIFORecordObjectPipe(ControlBase): def elaborate(self, platform): - m = ControlBase._elaborate(self, platform) + m = ControlBase.elaborate(self, platform) pipe1 = FIFOTestRecordControl() pipe2 = ExampleRecordHandshakeAddClass() @@ -891,7 +895,7 @@ class FIFOTestAdd16(FIFOControl): class ExampleFIFOAdd2Pipe(ControlBase): def elaborate(self, platform): - m = ControlBase._elaborate(self, platform) + m = ControlBase.elaborate(self, platform) pipe1 = FIFOTestAdd16() pipe2 = FIFOTestAdd16() @@ -925,7 +929,7 @@ class FIFOTest2x16(FIFOControl): class ExampleBufPassThruPipe2(ControlBase): def elaborate(self, platform): - m = ControlBase._elaborate(self, platform) + m = ControlBase.elaborate(self, platform) # XXX currently fails: any other permutation works fine. # p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok @@ -953,7 +957,7 @@ class ExampleBufPipe3(ControlBase): """ def elaborate(self, platform): - m = ControlBase._elaborate(self, platform) + m = ControlBase.elaborate(self, platform) pipe1 = ExampleBufDelayedPipe() pipe2 = ExampleBufPipe() @@ -987,7 +991,7 @@ class ExampleUnBufAdd1Pipe(UnbufferedPipeline): class ExampleBufUnBufPipe(ControlBase): def elaborate(self, platform): - m = ControlBase._elaborate(self, platform) + m = ControlBase.elaborate(self, platform) # XXX currently fails: any other permutation works fine. # p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok @@ -1020,9 +1024,9 @@ if __name__ == '__main__': print ("test 2") dut = ExampleBufPipe2() run_simulation(dut, tbench2(dut), vcd_name="test_bufpipe2.vcd") - ports = [dut.p.i_valid, dut.n.i_ready, - dut.n.o_valid, dut.p.o_ready] + \ - [dut.p.i_data] + [dut.n.o_data] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] vl = rtlil.convert(dut, ports=ports) with open("test_bufpipe2.il", "w") as f: f.write(vl) @@ -1052,9 +1056,9 @@ if __name__ == '__main__': test = Test5(dut, resultfn_6) run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltcomb6.vcd") - ports = [dut.p.i_valid, dut.n.i_ready, - dut.n.o_valid, dut.p.o_ready] + \ - list(dut.p.i_data) + [dut.n.o_data] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + list(dut.p.data_i) + [dut.n.data_o] vl = rtlil.convert(dut, ports=ports) with open("test_ltcomb_pipe.il", "w") as f: f.write(vl) @@ -1063,10 +1067,10 @@ if __name__ == '__main__': dut = ExampleAddRecordPipe() data=data_dict() test = Test5(dut, resultfn_7, data=data) - ports = [dut.p.i_valid, dut.n.i_ready, - dut.n.o_valid, dut.p.o_ready, - dut.p.i_data.src1, dut.p.i_data.src2, - dut.n.o_data.src1, dut.n.o_data.src2] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o, + dut.p.data_i.src1, dut.p.data_i.src2, + dut.n.data_o.src1, dut.n.data_o.src2] vl = rtlil.convert(dut, ports=ports) with open("test_recordcomb_pipe.il", "w") as f: f.write(vl) @@ -1080,9 +1084,9 @@ if __name__ == '__main__': print ("test 9") dut = ExampleBufPipeChain2() - ports = [dut.p.i_valid, dut.n.i_ready, - dut.n.o_valid, dut.p.o_ready] + \ - [dut.p.i_data] + [dut.n.o_data] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] vl = rtlil.convert(dut, ports=ports) with open("test_bufpipechain2.il", "w") as f: f.write(vl) @@ -1112,9 +1116,9 @@ if __name__ == '__main__': data = data_chain1() test = Test5(dut, resultfn_12, data=data) run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe12.vcd") - ports = [dut.p.i_valid, dut.n.i_ready, - dut.n.o_valid, dut.p.o_ready] + \ - [dut.p.i_data] + [dut.n.o_data] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] vl = rtlil.convert(dut, ports=ports) with open("test_bufpipe12.il", "w") as f: f.write(vl) @@ -1124,9 +1128,9 @@ if __name__ == '__main__': data = data_chain1() test = Test5(dut, resultfn_12, data=data) run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe13.vcd") - ports = [dut.p.i_valid, dut.n.i_ready, - dut.n.o_valid, dut.p.o_ready] + \ - [dut.p.i_data] + [dut.n.o_data] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] vl = rtlil.convert(dut, ports=ports) with open("test_unbufpipe13.il", "w") as f: f.write(vl) @@ -1136,9 +1140,9 @@ if __name__ == '__main__': data = data_chain1() test = Test5(dut, resultfn_12, data=data) run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf15.vcd") - ports = [dut.p.i_valid, dut.n.i_ready, - dut.n.o_valid, dut.p.o_ready] + \ - [dut.p.i_data] + [dut.n.o_data] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] vl = rtlil.convert(dut, ports=ports) with open("test_bufunbuf15.il", "w") as f: f.write(vl) @@ -1148,9 +1152,9 @@ if __name__ == '__main__': data = data_chain1() test = Test5(dut, resultfn_9, data=data) run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf16.vcd") - ports = [dut.p.i_valid, dut.n.i_ready, - dut.n.o_valid, dut.p.o_ready] + \ - [dut.p.i_data] + [dut.n.o_data] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] vl = rtlil.convert(dut, ports=ports) with open("test_bufunbuf16.il", "w") as f: f.write(vl) @@ -1160,9 +1164,9 @@ if __name__ == '__main__': data = data_chain1() test = Test5(dut, resultfn_12, data=data) run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe17.vcd") - ports = [dut.p.i_valid, dut.n.i_ready, - dut.n.o_valid, dut.p.o_ready] + \ - [dut.p.i_data] + [dut.n.o_data] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] vl = rtlil.convert(dut, ports=ports) with open("test_unbufpipe17.il", "w") as f: f.write(vl) @@ -1172,9 +1176,9 @@ if __name__ == '__main__': data = data_chain1() test = Test5(dut, resultfn_identical, data=data) run_simulation(dut, [test.send, test.rcv], vcd_name="test_passthru18.vcd") - ports = [dut.p.i_valid, dut.n.i_ready, - dut.n.o_valid, dut.p.o_ready] + \ - [dut.p.i_data] + [dut.n.o_data] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] vl = rtlil.convert(dut, ports=ports) with open("test_passthru18.il", "w") as f: f.write(vl) @@ -1184,9 +1188,9 @@ if __name__ == '__main__': data = data_chain1() test = Test5(dut, resultfn_9, data=data) run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass19.vcd") - ports = [dut.p.i_valid, dut.n.i_ready, - dut.n.o_valid, dut.p.o_ready] + \ - [dut.p.i_data] + [dut.n.o_data] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] vl = rtlil.convert(dut, ports=ports) with open("test_bufpass19.il", "w") as f: f.write(vl) @@ -1196,9 +1200,9 @@ if __name__ == '__main__': data = data_chain1() test = Test5(dut, resultfn_identical, data=data) run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifo20.vcd") - ports = [dut.p.i_valid, dut.n.i_ready, - dut.n.o_valid, dut.p.o_ready] + \ - [dut.p.i_data] + [dut.n.o_data] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] vl = rtlil.convert(dut, ports=ports) with open("test_fifo20.il", "w") as f: f.write(vl) @@ -1208,9 +1212,9 @@ if __name__ == '__main__': data = data_chain1() test = Test5(dut, resultfn_12, data=data) run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifopass21.vcd") - ports = [dut.p.i_valid, dut.n.i_ready, - dut.n.o_valid, dut.p.o_ready] + \ - [dut.p.i_data] + [dut.n.o_data] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] vl = rtlil.convert(dut, ports=ports) with open("test_fifopass21.il", "w") as f: f.write(vl) @@ -1220,10 +1224,10 @@ if __name__ == '__main__': data=data_2op() test = Test5(dut, resultfn_8, data=data) run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord22.vcd") - ports = [dut.p.i_valid, dut.n.i_ready, - dut.n.o_valid, dut.p.o_ready] + \ - [dut.p.i_data.op1, dut.p.i_data.op2] + \ - [dut.n.o_data] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i.op1, dut.p.data_i.op2] + \ + [dut.n.data_o] vl = rtlil.convert(dut, ports=ports) with open("test_addrecord22.il", "w") as f: f.write(vl) @@ -1233,10 +1237,10 @@ if __name__ == '__main__': data=data_2op() test = Test5(dut, resultfn_8, data=data) run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord23.vcd") - ports = [dut.p.i_valid, dut.n.i_ready, - dut.n.o_valid, dut.p.o_ready] + \ - [dut.p.i_data.op1, dut.p.i_data.op2] + \ - [dut.n.o_data] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i.op1, dut.p.data_i.op2] + \ + [dut.n.data_o] vl = rtlil.convert(dut, ports=ports) with open("test_addrecord23.il", "w") as f: f.write(vl) @@ -1245,10 +1249,10 @@ if __name__ == '__main__': dut = FIFOTestRecordAddStageControl() data=data_2op() test = Test5(dut, resultfn_8, data=data) - ports = [dut.p.i_valid, dut.n.i_ready, - dut.n.o_valid, dut.p.o_ready] + \ - [dut.p.i_data.op1, dut.p.i_data.op2] + \ - [dut.n.o_data] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i.op1, dut.p.data_i.op2] + \ + [dut.n.data_o] vl = rtlil.convert(dut, ports=ports) with open("test_addrecord24.il", "w") as f: f.write(vl) @@ -1259,9 +1263,9 @@ if __name__ == '__main__': data = data_chain1() test = Test5(dut, resultfn_9, data=data) run_simulation(dut, [test.send, test.rcv], vcd_name="test_add2pipe25.vcd") - ports = [dut.p.i_valid, dut.n.i_ready, - dut.n.o_valid, dut.p.o_ready] + \ - [dut.p.i_data] + [dut.n.o_data] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] vl = rtlil.convert(dut, ports=ports) with open("test_add2pipe25.il", "w") as f: f.write(vl) @@ -1271,9 +1275,9 @@ if __name__ == '__main__': data = data_chain1() test = Test5(dut, resultfn_9, data=data) run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass997.vcd") - ports = [dut.p.i_valid, dut.n.i_ready, - dut.n.o_valid, dut.p.o_ready] + \ - [dut.p.i_data] + [dut.n.o_data] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] vl = rtlil.convert(dut, ports=ports) with open("test_bufpass997.il", "w") as f: f.write(vl) @@ -1283,9 +1287,9 @@ if __name__ == '__main__': data = data_chain1() test = Test5(dut, resultfn_9, data=data) run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe14.vcd") - ports = [dut.p.i_valid, dut.n.i_ready, - dut.n.o_valid, dut.p.o_ready] + \ - [dut.p.i_data] + [dut.n.o_data] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] vl = rtlil.convert(dut, ports=ports) with open("test_bufpipe14.il", "w") as f: f.write(vl) @@ -1295,9 +1299,9 @@ if __name__ == '__main__': data = data_chain1() test = Test5(dut, resultfn_9, data=data) run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf999.vcd") - ports = [dut.p.i_valid, dut.n.i_ready, - dut.n.o_valid, dut.p.o_ready] + \ - [dut.p.i_data] + [dut.n.o_data] + ports = [dut.p.valid_i, dut.n.ready_i, + dut.n.valid_o, dut.p.ready_o] + \ + [dut.p.data_i] + [dut.n.data_o] vl = rtlil.convert(dut, ports=ports) with open("test_bufunbuf999.il", "w") as f: f.write(vl)