X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Ftest_buf_pipe.py;h=baa344a91faa442b4b93d87d878f9db687ca3152;hb=0bfbc8ff919f0cd9c7f01b4c711b1b91a53ad480;hp=860f25cb114e2f5920edd69a9c468d3b506c00cc;hpb=2ec9fee974fe500ff4e3375d35f6148ef3560e36;p=ieee754fpu.git

diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 860f25cb..baa344a9 100644
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -5,20 +5,24 @@ from random import randint
 
 
 def check_o_n_stb(dut, val):
+    o_n_stb = yield dut.o.n_stb
+    assert o_n_stb == val
+
+def check_o_n_stb2(dut, val):
     o_n_stb = yield dut.o_n_stb
     assert o_n_stb == val
 
 
 def testbench(dut):
     #yield dut.i_p_rst.eq(1)
-    yield dut.i_n_busy.eq(1)
-    yield dut.o_p_busy.eq(1)
+    yield dut.i.n_busy.eq(1)
+    yield dut.o.p_busy.eq(1)
     yield
     yield
     #yield dut.i_p_rst.eq(0)
-    yield dut.i_n_busy.eq(0)
+    yield dut.i.n_busy.eq(0)
     yield dut.stage.i_data.eq(5)
-    yield dut.i_p_stb.eq(1)
+    yield dut.i.p_stb.eq(1)
     yield
 
     yield dut.stage.i_data.eq(7)
@@ -28,14 +32,14 @@ def testbench(dut):
 
     yield dut.stage.i_data.eq(2)
     yield
-    yield dut.i_n_busy.eq(1) # begin going into "stall" (next stage says busy)
+    yield dut.i.n_busy.eq(1) # begin going into "stall" (next stage says busy)
     yield dut.stage.i_data.eq(9)
     yield
-    yield dut.i_p_stb.eq(0)
+    yield dut.i.p_stb.eq(0)
     yield dut.stage.i_data.eq(12)
     yield
     yield dut.stage.i_data.eq(32)
-    yield dut.i_n_busy.eq(0)
+    yield dut.i.n_busy.eq(0)
     yield
     yield from check_o_n_stb(dut, 1) # buffer still needs to output
     yield
@@ -46,25 +50,25 @@ def testbench(dut):
 
 
 def testbench2(dut):
-    #yield dut.i_p_rst.eq(1)
+    #yield dut.i.p_rst.eq(1)
     yield dut.i_n_busy.eq(1)
-    #yield dut.o_p_busy.eq(1)
+    #yield dut.o.p_busy.eq(1)
     yield
     yield
-    #yield dut.i_p_rst.eq(0)
+    #yield dut.i.p_rst.eq(0)
     yield dut.i_n_busy.eq(0)
     yield dut.i_data.eq(5)
     yield dut.i_p_stb.eq(1)
     yield
 
     yield dut.i_data.eq(7)
-    yield from check_o_n_stb(dut, 0) # effects of i_p_stb delayed 2 clocks
+    yield from check_o_n_stb2(dut, 0) # effects of i_p_stb delayed 2 clocks
     yield
-    yield from check_o_n_stb(dut, 0) # effects of i_p_stb delayed 2 clocks
+    yield from check_o_n_stb2(dut, 0) # effects of i_p_stb delayed 2 clocks
 
     yield dut.i_data.eq(2)
     yield
-    yield from check_o_n_stb(dut, 1) # ok *now* i_p_stb effect is felt
+    yield from check_o_n_stb2(dut, 1) # ok *now* i_p_stb effect is felt
     yield dut.i_n_busy.eq(1) # begin going into "stall" (next stage says busy)
     yield dut.i_data.eq(9)
     yield
@@ -74,52 +78,71 @@ def testbench2(dut):
     yield dut.i_data.eq(32)
     yield dut.i_n_busy.eq(0)
     yield
-    yield from check_o_n_stb(dut, 1) # buffer still needs to output
-    yield
-    yield from check_o_n_stb(dut, 1) # buffer still needs to output
-    yield
-    yield from check_o_n_stb(dut, 1) # buffer still needs to output
-    yield
-    yield from check_o_n_stb(dut, 0) # buffer outputted, *now* we're done.
-    yield
-    yield
-    yield
-
-
-def testbench3(dut):
-    data = []
-    for i in range(1000):
-        #data.append(randint(0, 1<<16-1))
-        data.append(i+1)
-    i = 0
-    o = 0
-    while True:
-        stall = randint(0, 3) == 0
-        send = randint(0, 5) != 0
-        yield dut.i_n_busy.eq(stall)
-        o_p_busy = yield dut.o_p_busy
-        if not o_p_busy:
-            if send and i != len(data):
-                yield dut.i_p_stb.eq(1)
-                yield dut.stage.i_data.eq(data[i])
-                i += 1
-            else:
-                yield dut.i_p_stb.eq(0)
-        yield
-        o_n_stb = yield dut.o_n_stb
-        i_n_busy = yield dut.i_n_busy
-        if o_n_stb and not i_n_busy:
-            o_data = yield dut.stage.o_data
-            assert o_data == data[o] + 1, "%d-%d data %x not match %x\n" \
-                                        % (i, o, o_data, data[o])
-            o += 1
-            if o == len(data):
-                break
+    yield from check_o_n_stb2(dut, 1) # buffer still needs to output
+    yield
+    yield from check_o_n_stb2(dut, 1) # buffer still needs to output
+    yield
+    yield from check_o_n_stb2(dut, 1) # buffer still needs to output
+    yield
+    yield from check_o_n_stb2(dut, 0) # buffer outputted, *now* we're done.
+    yield
+    yield
+    yield
+
+
+class Test3:
+    def __init__(self, dut):
+        self.dut = dut
+        self.data = []
+        for i in range(10000):
+            #data.append(randint(0, 1<<16-1))
+            self.data.append(i+1)
+        self.i = 0
+        self.o = 0
+
+    def send(self):
+        while self.o != len(self.data):
+            send_range = randint(0, 3)
+            for j in range(randint(1,10)):
+                if send_range == 0:
+                    send = True
+                else:
+                    send = randint(0, send_range) != 0
+                o_p_busy = yield self.dut.o.p_busy
+                if o_p_busy:
+                    yield
+                    continue
+                if send and self.i != len(self.data):
+                    yield self.dut.i.p_stb.eq(1)
+                    yield self.dut.stage.i_data.eq(self.data[self.i])
+                    self.i += 1
+                else:
+                    yield self.dut.i.p_stb.eq(0)
+                yield
+
+    def rcv(self):
+        while self.o != len(self.data):
+            stall_range = randint(0, 3)
+            for j in range(randint(1,10)):
+                stall = randint(0, stall_range) == 0
+                yield self.dut.i.n_busy.eq(stall)
+                yield
+                o_n_stb = yield self.dut.o.n_stb
+                i_n_busy = yield self.dut.i.n_busy
+                if not o_n_stb or i_n_busy:
+                    continue
+                o_data = yield self.dut.stage.o_data
+                assert o_data == self.data[self.o] + 1, \
+                            "%d-%d data %x not match %x\n" \
+                            % (self.i, self.o, o_data, self.data[self.o])
+                self.o += 1
+                if self.o == len(self.data):
+                    break
 
 
 def testbench4(dut):
     data = []
-    for i in range(1000):
+    for i in range(10000):
         #data.append(randint(0, 1<<16-1))
         data.append(i+1)
     i = 0
@@ -176,31 +199,36 @@ class BufPipe2:
         m.submodules.pipe2 = self.pipe2
 
         # connect inter-pipe input/output stb/busy/data
-        m.d.comb += self.pipe2.i_p_stb.eq(self.pipe1.o_n_stb)
-        m.d.comb += self.pipe1.i_n_busy.eq(self.pipe2.o_p_busy)
+        m.d.comb += self.pipe2.i.p_stb.eq(self.pipe1.o.n_stb)
+        m.d.comb += self.pipe1.i.n_busy.eq(self.pipe2.o.p_busy)
         m.d.comb += self.pipe2.stage.i_data.eq(self.pipe1.stage.o_data)
 
         # inputs/outputs to the module: pipe1 connections here (LHS)
-        m.d.comb += self.pipe1.i_p_stb.eq(self.i_p_stb)
-        m.d.comb += self.o_p_busy.eq(self.pipe1.o_p_busy)
+        m.d.comb += self.pipe1.i.p_stb.eq(self.i_p_stb)
+        m.d.comb += self.o_p_busy.eq(self.pipe1.o.p_busy)
         m.d.comb += self.pipe1.stage.i_data.eq(self.i_data)
 
         # now pipe2 connections (RHS)
-        m.d.comb += self.o_n_stb.eq(self.pipe2.o_n_stb)
-        m.d.comb += self.pipe2.i_n_busy.eq(self.i_n_busy)
+        m.d.comb += self.o_n_stb.eq(self.pipe2.o.n_stb)
+        m.d.comb += self.pipe2.i.n_busy.eq(self.i_n_busy)
         m.d.comb += self.o_data.eq(self.pipe2.stage.o_data)
 
         return m
 
 if __name__ == '__main__':
+    print ("test 1")
     dut = BufPipe()
     run_simulation(dut, testbench(dut), vcd_name="test_bufpipe.vcd")
 
+    print ("test 2")
     dut = BufPipe2()
     run_simulation(dut, testbench2(dut), vcd_name="test_bufpipe2.vcd")
 
+    print ("test 3")
     dut = BufPipe()
-    run_simulation(dut, testbench3(dut), vcd_name="test_bufpipe3.vcd")
+    test = Test3(dut)
+    run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe3.vcd")
 
+    print ("test 4")
     dut = BufPipe2()
     run_simulation(dut, testbench4(dut), vcd_name="test_bufpipe4.vcd")