X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Ftest_buf_pipe.py;h=e38043ecd7775959e65a15341c83b5636a895748;hb=f3945d1317aa236b752c1e286801caa2c3a07703;hp=76c71a8332f44142cf518c3200536b2b817160ac;hpb=837eb17472ba4f9cc43f47d0939415a6b9ad61ab;p=ieee754fpu.git

diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 76c71a83..e38043ec 100644
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -1,8 +1,13 @@
 from nmigen import Module, Signal, Mux
+from nmigen.hdl.rec import Record
 from nmigen.compat.sim import run_simulation
+from nmigen.cli import verilog, rtlil
+
 from example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
-from example_buf_pipe import ExampleCombPipe, CombPipe
-from example_buf_pipe import PrevControl, NextControl
+from example_buf_pipe import ExampleCombPipe, CombPipe, ExampleStageCls
+from example_buf_pipe import PrevControl, NextControl, BufferedPipeline
+from example_buf_pipe import StageChain
+
 from random import randint
 
 
@@ -19,24 +24,24 @@ def testbench(dut):
     yield
     #yield dut.i_p_rst.eq(0)
     yield dut.n.i_ready.eq(1)
-    yield dut.p.data.eq(5)
+    yield dut.p.i_data.eq(5)
     yield dut.p.i_valid.eq(1)
     yield
 
-    yield dut.p.data.eq(7)
+    yield dut.p.i_data.eq(7)
     yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed
     yield
     yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt
 
-    yield dut.p.data.eq(2)
+    yield dut.p.i_data.eq(2)
     yield
     yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
-    yield dut.p.data.eq(9)
+    yield dut.p.i_data.eq(9)
     yield
     yield dut.p.i_valid.eq(0)
-    yield dut.p.data.eq(12)
+    yield dut.p.i_data.eq(12)
     yield
-    yield dut.p.data.eq(32)
+    yield dut.p.i_data.eq(32)
     yield dut.n.i_ready.eq(1)
     yield
     yield from check_o_n_valid(dut, 1) # buffer still needs to output
@@ -55,25 +60,25 @@ def testbench2(dut):
     yield
     #yield dut.p.i_rst.eq(0)
     yield dut.n.i_ready.eq(1)
-    yield dut.p.data.eq(5)
+    yield dut.p.i_data.eq(5)
     yield dut.p.i_valid.eq(1)
     yield
 
-    yield dut.p.data.eq(7)
+    yield dut.p.i_data.eq(7)
     yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed 2 clocks
     yield
     yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed 2 clocks
 
-    yield dut.p.data.eq(2)
+    yield dut.p.i_data.eq(2)
     yield
     yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt
     yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
-    yield dut.p.data.eq(9)
+    yield dut.p.i_data.eq(9)
     yield
     yield dut.p.i_valid.eq(0)
-    yield dut.p.data.eq(12)
+    yield dut.p.i_data.eq(12)
     yield
-    yield dut.p.data.eq(32)
+    yield dut.p.i_data.eq(32)
     yield dut.n.i_ready.eq(1)
     yield
     yield from check_o_n_valid(dut, 1) # buffer still needs to output
@@ -113,7 +118,7 @@ class Test3:
                     continue
                 if send and self.i != len(self.data):
                     yield self.dut.p.i_valid.eq(1)
-                    yield self.dut.p.data.eq(self.data[self.i])
+                    yield self.dut.p.i_data.eq(self.data[self.i])
                     self.i += 1
                 else:
                     yield self.dut.p.i_valid.eq(0)
@@ -130,7 +135,7 @@ class Test3:
                 i_n_ready = yield self.dut.n.i_ready
                 if not o_n_valid or not i_n_ready:
                     continue
-                o_data = yield self.dut.n.data
+                o_data = yield self.dut.n.o_data
                 self.resultfn(o_data, self.data[self.o], self.i, self.o)
                 self.o += 1
                 if self.o == len(self.data):
@@ -141,13 +146,24 @@ def test3_resultfn(o_data, expected, i, o):
                 "%d-%d data %x not match %x\n" \
                 % (i, o, o_data, expected)
 
+def data_dict():
+        data = []
+        for i in range(num_tests):
+            data.append({'src1': randint(0, 1<<16-1),
+                         'src2': randint(0, 1<<16-1)})
+        return data
+
+
 class Test5:
-    def __init__(self, dut, resultfn):
+    def __init__(self, dut, resultfn, data=None):
         self.dut = dut
         self.resultfn = resultfn
-        self.data = []
-        for i in range(num_tests):
-            self.data.append((randint(0, 1<<16-1), randint(0, 1<<16-1)))
+        if data:
+            self.data = data
+        else:
+            self.data = []
+            for i in range(num_tests):
+                self.data.append((randint(0, 1<<16-1), randint(0, 1<<16-1)))
         self.i = 0
         self.o = 0
 
@@ -183,7 +199,13 @@ class Test5:
                 i_n_ready = yield self.dut.n.i_ready
                 if not o_n_valid or not i_n_ready:
                     continue
-                o_data = yield self.dut.n.data
+                if isinstance(self.dut.n.o_data, Record):
+                    o_data = {}
+                    dod = self.dut.n.o_data
+                    for k, v in dod.fields.items():
+                        o_data[k] = yield v
+                else:
+                    o_data = yield self.dut.n.o_data
                 self.resultfn(o_data, self.data[self.o], self.i, self.o)
                 self.o += 1
                 if self.o == len(self.data):
@@ -210,7 +232,7 @@ def testbench4(dut):
         if o_p_ready:
             if send and i != len(data):
                 yield dut.p.i_valid.eq(1)
-                yield dut.p.data.eq(data[i])
+                yield dut.p.i_data.eq(data[i])
                 i += 1
             else:
                 yield dut.p.i_valid.eq(0)
@@ -218,7 +240,7 @@ def testbench4(dut):
         o_n_valid = yield dut.n.o_valid
         i_n_ready = yield dut.n.i_ready
         if o_n_valid and i_n_ready:
-            o_data = yield dut.n.data
+            o_data = yield dut.n.o_data
             assert o_data == data[o] + 2, "%d-%d data %x not match %x\n" \
                                         % (i, o, o_data, data[o])
             o += 1
@@ -232,7 +254,7 @@ class ExampleBufPipe2:
                               v               v
         i_p_valid >>in  pipe1 o_n_valid out>> i_p_valid >>in  pipe2
         o_p_ready <<out pipe1 i_n_ready <<in  o_p_ready <<out pipe2
-        p_data    >>in  pipe1 o_data    out>> p_data    >>in  pipe2
+        p_i_data  >>in  pipe1 p_i_data  out>> n_o_data  >>in  pipe2
     """
     def __init__(self):
         self.pipe1 = ExampleBufPipe()
@@ -240,11 +262,11 @@ class ExampleBufPipe2:
 
         # input
         self.p = PrevControl()
-        self.p.data = Signal(32) # >>in - comes in from the PREVIOUS stage
+        self.p.i_data = Signal(32) # >>in - comes in from the PREVIOUS stage
 
         # output
         self.n = NextControl()
-        self.n.data = Signal(32) # out>> - goes out to the NEXT stage
+        self.n.o_data = Signal(32) # out>> - goes out to the NEXT stage
 
     def elaborate(self, platform):
         m = Module()
@@ -252,7 +274,7 @@ class ExampleBufPipe2:
         m.submodules.pipe2 = self.pipe2
 
         # connect inter-pipe input/output valid/ready/data
-        m.d.comb += self.pipe1.connect_next(self.pipe2)
+        m.d.comb += self.pipe1.connect_to_next(self.pipe2)
 
         # inputs/outputs to the module: pipe1 connections here (LHS)
         m.d.comb += self.pipe1.connect_in(self)
@@ -262,6 +284,31 @@ class ExampleBufPipe2:
 
         return m
 
+
+class ExampleBufPipeChain2(BufferedPipeline):
+    """ connects two stages together as a *single* combinatorial stage.
+    """
+    def __init__(self):
+        stage1 = ExampleStageCls()
+        stage2 = ExampleStageCls()
+        combined = StageChain([stage1, stage2])
+        BufferedPipeline.__init__(self, combined)
+
+
+def data_chain2():
+        data = []
+        for i in range(num_tests):
+            data.append(randint(0, 1<<16-2))
+        return data
+
+
+def test9_resultfn(o_data, expected, i, o):
+    res = expected + 2
+    assert o_data == res, \
+                "%d-%d data %x not match %s\n" \
+                % (i, o, o_data, repr(expected))
+
+
 class SetLessThan:
     def __init__(self, width, signed):
         self.src1 = Signal((width, signed))
@@ -311,7 +358,110 @@ def test6_resultfn(o_data, expected, i, o):
                 % (i, o, o_data, repr(expected))
 
 
-num_tests = 1000
+class ExampleAddRecordStage:
+    """ example use of a Record
+    """
+
+    record_spec = [('src1', 16), ('src2', 16)]
+    def ispec(self):
+        """ returns a tuple of input signals which will be the incoming data
+        """
+        return Record(self.record_spec)
+
+    def ospec(self):
+        return Record(self.record_spec)
+
+    def process(self, i):
+        """ process the input data (sums the values in the tuple) and returns it
+        """
+        return {'src1': i.src1 + 1,
+                'src2': i.src2 + 1}
+
+
+class ExampleAddRecordPipe(CombPipe):
+    """ an example of how to use the combinatorial pipeline.
+    """
+
+    def __init__(self):
+        stage = ExampleAddRecordStage()
+        CombPipe.__init__(self, stage)
+
+
+def test7_resultfn(o_data, expected, i, o):
+    res = (expected['src1'] + 1, expected['src2'] + 1)
+    assert o_data['src1'] == res[0] and o_data['src2'] == res[1], \
+                "%d-%d data %s not match %s\n" \
+                % (i, o, repr(o_data), repr(expected))
+
+
+class Example2OpClass:
+    """ an example of a class used to store 2 operands.
+        requires an eq function, to conform with the pipeline stage API
+    """
+
+    def __init__(self):
+        self.op1 = Signal(16)
+        self.op2 = Signal(16)
+
+    def eq(self, i):
+        return [self.op1.eq(i.op1), self.op2.eq(i.op2)]
+
+
+class ExampleAddClassStage:
+    """ an example of how to use the buffered pipeline, as a class instance
+    """
+
+    def ispec(self):
+        """ returns an instance of an Example2OpClass.
+        """
+        return Example2OpClass()
+
+    def ospec(self):
+        """ returns an output signal which will happen to contain the sum
+            of the two inputs
+        """
+        return Signal(16)
+
+    def process(self, i):
+        """ process the input data (sums the values in the tuple) and returns it
+        """
+        return i.op1 + i.op2
+
+
+class ExampleBufPipeAddClass(BufferedPipeline):
+    """ an example of how to use the buffered pipeline, using a class instance
+    """
+
+    def __init__(self):
+        addstage = ExampleAddClassStage()
+        BufferedPipeline.__init__(self, addstage)
+
+
+class TestInputAdd:
+    """ the eq function, called by set_input, needs an incoming object
+        that conforms to the Example2OpClass.eq function requirements
+        easiest way to do that is to create a class that has the exact
+        same member layout (self.op1, self.op2) as Example2OpClass
+    """
+    def __init__(self, op1, op2):
+        self.op1 = op1
+        self.op2 = op2
+
+
+def test8_resultfn(o_data, expected, i, o):
+    res = expected.op1 + expected.op2 # these are a TestInputAdd instance
+    assert o_data == res, \
+                "%d-%d data %x not match %s\n" \
+                % (i, o, o_data, repr(expected))
+
+def data_2op():
+        data = []
+        for i in range(num_tests):
+            data.append(TestInputAdd(randint(0, 1<<16-1), randint(0, 1<<16-1)))
+        return data
+
+
+num_tests = 100
 
 if __name__ == '__main__':
     print ("test 1")
@@ -346,3 +496,44 @@ if __name__ == '__main__':
     test = Test5(dut, test6_resultfn)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltcomb6.vcd")
 
+    ports = [dut.p.i_valid, dut.n.i_ready,
+             dut.n.o_valid, dut.p.o_ready] + \
+             list(dut.p.i_data) + [dut.n.o_data]
+    vl = rtlil.convert(dut, ports=ports)
+    with open("test_ltcomb_pipe.il", "w") as f:
+        f.write(vl)
+
+    print ("test 7")
+    dut = ExampleAddRecordPipe()
+    data=data_dict()
+    test = Test5(dut, test7_resultfn, data=data)
+    run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord.vcd")
+
+    ports = [dut.p.i_valid, dut.n.i_ready,
+             dut.n.o_valid, dut.p.o_ready,
+             dut.p.i_data.src1, dut.p.i_data.src2,
+             dut.n.o_data.src1, dut.n.o_data.src2]
+    vl = rtlil.convert(dut, ports=ports)
+    with open("test_recordcomb_pipe.il", "w") as f:
+        f.write(vl)
+
+    print ("test 8")
+    dut = ExampleBufPipeAddClass()
+    data=data_2op()
+    test = Test5(dut, test8_resultfn, data=data)
+    run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe8.vcd")
+
+    print ("test 9")
+    dut = ExampleBufPipeChain2()
+    ports = [dut.p.i_valid, dut.n.i_ready,
+             dut.n.o_valid, dut.p.o_ready] + \
+             [dut.p.i_data] + [dut.n.o_data]
+    vl = rtlil.convert(dut, ports=ports)
+    with open("test_bufpipechain2.il", "w") as f:
+        f.write(vl)
+
+    data = data_chain2()
+    test = Test5(dut, test9_resultfn, data=data)
+    run_simulation(dut, [test.send, test.rcv],
+                        vcd_name="test_bufpipechain2.vcd")
+