X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Ftest_fsm_experiment.py;h=17cee24ebb4cb5e85cd49311140017912f4488df;hb=6bff1a997f3846872cf489c24b5c01426c4dc97c;hp=b40bb63f0445a3e2ad080be4d8b8f9319f8330f7;hpb=d13255e03e4506d8ae68d19f37052d83f00694b5;p=ieee754fpu.git

diff --git a/src/add/test_fsm_experiment.py b/src/add/test_fsm_experiment.py
index b40bb63f..17cee24e 100644
--- a/src/add/test_fsm_experiment.py
+++ b/src/add/test_fsm_experiment.py
@@ -19,11 +19,26 @@ class FPDIV(FPBase, Elaboratable):
         FPBase.__init__(self)
         self.width = width
 
-        self.in_a  = FPOpIn(width)
-        self.out_z = FPOpOut(width)
+        self.p = FPOpIn(width)
+        self.n = FPOpOut(width)
+
+        self.p.data_i = self.ispec()
+        self.n.data_o = self.ospec()
 
         self.states = []
 
+    def ispec(self):
+        return Signal(self.width, name="a")
+
+    def ospec(self):
+        return Signal(self.width, name="z")
+
+    def setup(self, m, i):
+        m.d.comb += self.p.v.eq(i) # connect input
+
+    def process(self, i):
+        return self.n.v # return z output
+
     def add_state(self, state):
         self.states.append(state)
         return state
@@ -37,12 +52,12 @@ class FPDIV(FPBase, Elaboratable):
         a = FPNumIn(None, self.width, False)
         z = FPNumOut(self.width, False)
 
-        m.submodules.in_a = self.in_a
-        m.submodules.out_z = self.out_z
+        m.submodules.p = self.p
+        m.submodules.n = self.n
         m.submodules.a = a
         m.submodules.z = z
 
-        m.d.comb += a.v.eq(self.in_a.v)
+        m.d.comb += a.v.eq(self.p.v)
 
         with m.FSM() as fsm:
 
@@ -50,8 +65,8 @@ class FPDIV(FPBase, Elaboratable):
             # gets operand a
 
             with m.State("get_a"):
-                res = self.get_op(m, self.in_a, a, "add_1")
-                m.d.sync += eq([a, self.in_a.ready_o], res)
+                res = self.get_op(m, self.p, a, "add_1")
+                m.d.sync += eq([a, self.p.ready_o], res)
 
             with m.State("add_1"):
                 m.next = "pack"
@@ -71,7 +86,7 @@ class FPDIV(FPBase, Elaboratable):
             # put_z stage
 
             with m.State("put_z"):
-                self.put_z(m, z, self.out_z, "get_a")
+                self.put_z(m, z, self.n, "get_a")
 
         return m
 
@@ -80,19 +95,7 @@ class FPDIVPipe(ControlBase):
     def __init__(self, width):
         self.width = width
         self.fpdiv = FPDIV(width=width)
-        ControlBase.__init__(self, self)
-
-    def ispec(self):
-        return Signal(self.width, name="a")
-
-    def ospec(self):
-        return Signal(self.width, name="z")
-
-    def setup(self, m, i):
-        m.d.comb += self.fpdiv.in_a.v.eq(i) # connect input
-
-    def process(self, i):
-        return self.fpdiv.out_z.v # return z output
+        ControlBase.__init__(self, self.fpdiv)
 
     def elaborate(self, platform):
         self.m = m = ControlBase.elaborate(self, platform)
@@ -100,12 +103,9 @@ class FPDIVPipe(ControlBase):
         m.submodules.fpdiv = self.fpdiv
 
         # see if connecting to stb/ack works
-        m.d.comb += self.p.ready_o.eq(self.fpdiv.in_a.ready_o)
-        m.d.comb += self.fpdiv.in_a.valid_i.eq(self.p.valid_i_test)
-
-        m.d.comb += self.n.valid_o.eq(self.fpdiv.out_z.valid_o)
-        m.d.comb += self.fpdiv.out_z.ready_i.eq(self.n.ready_i_test)
-        m.d.comb += self.n.data_o.eq(self.data)
+        m.d.comb += self.fpdiv.p._connect_in(self.p)
+        m.d.comb += self.fpdiv.n._connect_out(self.n, do_data=False)
+        m.d.comb += self.n.data_o.eq(self.data_r)
 
         return m