X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Ftest_inout_mux_pipe.py;h=35abe2eaf46b3aa148826b6821640cf39dfe2786;hb=6bff1a997f3846872cf489c24b5c01426c4dc97c;hp=92b6f53f3b724ca73567b63c8ec9952cae97494c;hpb=db1d38524e0a9216138c8fa6ce0dc28d7596d077;p=ieee754fpu.git

diff --git a/src/add/test_inout_mux_pipe.py b/src/add/test_inout_mux_pipe.py
index 92b6f53f..35abe2ea 100644
--- a/src/add/test_inout_mux_pipe.py
+++ b/src/add/test_inout_mux_pipe.py
@@ -7,36 +7,30 @@
 
 from random import randint
 from math import log
-from nmigen import Module, Signal, Cat, Value
+from nmigen import Module, Signal, Cat, Value, Elaboratable
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
 from multipipe import CombMultiOutPipeline, CombMuxOutPipe
 from multipipe import PriorityCombMuxInPipe
-from singlepipe import SimpleHandshake
+from singlepipe import SimpleHandshake, RecordObject, Object
 
 
-class PassData: # (Value):
+class PassData2(RecordObject):
     def __init__(self):
+        RecordObject.__init__(self)
         self.mid = Signal(2, reset_less=True)
         self.idx = Signal(8, reset_less=True)
         self.data = Signal(16, reset_less=True)
 
-    def _rhs_signals(self):
-        return self.ports()
 
-    def shape(self):
-        bits, sign = 0, False
-        for elem_bits, elem_sign in (elem.shape() for elem in self.ports()):
-            bits = max(bits, elem_bits + elem_sign)
-            sign = max(sign, elem_sign)
-        return bits, sign
-
-    def eq(self, i):
-        return [self.mid.eq(i.mid), self.idx.eq(i.idx), self.data.eq(i.data)]
+class PassData(Object):
+    def __init__(self):
+        Object.__init__(self)
+        self.mid = Signal(2, reset_less=True)
+        self.idx = Signal(8, reset_less=True)
+        self.data = Signal(16, reset_less=True)
 
-    def ports(self):
-        return [self.mid, self.idx, self.data]
 
 
 class PassThroughStage:
@@ -72,24 +66,24 @@ class InputTest:
         for i in range(self.tlen):
             op2 = self.di[mid][i]
             rs = dut.p[mid]
-            yield rs.i_valid.eq(1)
-            yield rs.i_data.data.eq(op2)
-            yield rs.i_data.idx.eq(i)
-            yield rs.i_data.mid.eq(mid)
+            yield rs.valid_i.eq(1)
+            yield rs.data_i.data.eq(op2)
+            yield rs.data_i.idx.eq(i)
+            yield rs.data_i.mid.eq(mid)
             yield
-            o_p_ready = yield rs.o_ready
+            o_p_ready = yield rs.ready_o
             while not o_p_ready:
                 yield
-                o_p_ready = yield rs.o_ready
+                o_p_ready = yield rs.ready_o
 
             print ("send", mid, i, hex(op2))
 
-            yield rs.i_valid.eq(0)
+            yield rs.valid_i.eq(0)
             # wait random period of time before queueing another value
             for i in range(randint(0, 3)):
                 yield
 
-        yield rs.i_valid.eq(0)
+        yield rs.valid_i.eq(0)
         yield
 
         print ("send ended", mid)
@@ -109,19 +103,19 @@ class InputTest:
             #stall_range = randint(0, 3)
             #for j in range(randint(1,10)):
             #    stall = randint(0, stall_range) != 0
-            #    yield self.dut.n[0].i_ready.eq(stall)
+            #    yield self.dut.n[0].ready_i.eq(stall)
             #    yield
             n = self.dut.n[mid]
-            yield n.i_ready.eq(1)
+            yield n.ready_i.eq(1)
             yield
-            o_n_valid = yield n.o_valid
-            i_n_ready = yield n.i_ready
+            o_n_valid = yield n.valid_o
+            i_n_ready = yield n.ready_i
             if not o_n_valid or not i_n_ready:
                 continue
 
-            out_mid = yield n.o_data.mid
-            out_i = yield n.o_data.idx
-            out_v = yield n.o_data.data
+            out_mid = yield n.data_o.mid
+            out_i = yield n.data_o.idx
+            out_v = yield n.data_o.data
 
             print ("recv", out_mid, out_i, hex(out_v))
 
@@ -163,23 +157,23 @@ class OutputTest:
             op2 = self.di[i][0]
             mid = self.di[i][1]
             rs = dut.p
-            yield rs.i_valid.eq(1)
-            yield rs.i_data.data.eq(op2)
-            yield rs.i_data.mid.eq(mid)
+            yield rs.valid_i.eq(1)
+            yield rs.data_i.data.eq(op2)
+            yield rs.data_i.mid.eq(mid)
             yield
-            o_p_ready = yield rs.o_ready
+            o_p_ready = yield rs.ready_o
             while not o_p_ready:
                 yield
-                o_p_ready = yield rs.o_ready
+                o_p_ready = yield rs.ready_o
 
             print ("send", mid, i, hex(op2))
 
-            yield rs.i_valid.eq(0)
+            yield rs.valid_i.eq(0)
             # wait random period of time before queueing another value
             for i in range(randint(0, 3)):
                 yield
 
-        yield rs.i_valid.eq(0)
+        yield rs.valid_i.eq(0)
 
 
 class TestMuxOutPipe(CombMuxOutPipe):
@@ -189,7 +183,7 @@ class TestMuxOutPipe(CombMuxOutPipe):
         CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
 
 
-class TestInOutPipe:
+class TestInOutPipe(Elaboratable):
     def __init__(self, num_rows=4):
         self.num_rows = num_rows
         self.inpipe = TestPriorityMuxPipe(num_rows) # fan-in (combinatorial)