X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Ftest_inputgroup.py;h=09a72e176179e66d94484eebd5b971b2d3566d5a;hb=6bff1a997f3846872cf489c24b5c01426c4dc97c;hp=e78090ea69fc4192422832ef9dbc04220fc67f33;hpb=2e7a71c40cc2fb2b89c1019939e15d04287d36cf;p=ieee754fpu.git

diff --git a/src/add/test_inputgroup.py b/src/add/test_inputgroup.py
index e78090ea..09a72e17 100644
--- a/src/add/test_inputgroup.py
+++ b/src/add/test_inputgroup.py
@@ -3,7 +3,7 @@ from nmigen import Module, Signal
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
-from nmigen_add_experiment import InputGroup
+from inputgroup import InputGroup
 
 
 def testbench(dut):