X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Fadd%2Fnmigen_div_experiment.py;h=a19decd5850b2c54c8205b2aeb89d8a8d8ebfb97;hb=c413b537ad80d8392a19975561b18063992a1939;hp=a7e215cb888817b750426af676a7825552dee431;hpb=58e455d3bd9b43d076468bf2b7b1f0784e5c4fd2;p=ieee754fpu.git

diff --git a/src/ieee754/add/nmigen_div_experiment.py b/src/ieee754/add/nmigen_div_experiment.py
index a7e215cb..a19decd5 100644
--- a/src/ieee754/add/nmigen_div_experiment.py
+++ b/src/ieee754/add/nmigen_div_experiment.py
@@ -6,7 +6,7 @@ from nmigen import Module, Signal, Const, Cat
 from nmigen.cli import main, verilog
 
 from fpbase import FPNumIn, FPNumOut, FPOpIn, FPOpOut, Overflow, FPBase, FPState
-from singlepipe import eq
+from nmutil.singlepipe import eq
 
 class Div:
     def __init__(self, width):