X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Fadd%2Ftest_inout_mux_pipe.py;h=221ece1db7f4b51ab7269f08c915b2ebba363fa1;hb=17920e72ea4e212030671b0077b16c0719fc5059;hp=35abe2eaf46b3aa148826b6821640cf39dfe2786;hpb=58e455d3bd9b43d076468bf2b7b1f0784e5c4fd2;p=ieee754fpu.git

diff --git a/src/ieee754/add/test_inout_mux_pipe.py b/src/ieee754/add/test_inout_mux_pipe.py
index 35abe2ea..221ece1d 100644
--- a/src/ieee754/add/test_inout_mux_pipe.py
+++ b/src/ieee754/add/test_inout_mux_pipe.py
@@ -11,9 +11,9 @@ from nmigen import Module, Signal, Cat, Value, Elaboratable
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
-from multipipe import CombMultiOutPipeline, CombMuxOutPipe
-from multipipe import PriorityCombMuxInPipe
-from singlepipe import SimpleHandshake, RecordObject, Object
+from nmutil.multipipe import CombMultiOutPipeline, CombMuxOutPipe
+from nmutil.multipipe import PriorityCombMuxInPipe
+from nmutil.singlepipe import SimpleHandshake, RecordObject, Object
 
 
 class PassData2(RecordObject):